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Re: [Qemu-arm] [PATCH] target-arm: Fix reset and migration of TTBCR(S)
From: |
Sergey Fedorov |
Subject: |
Re: [Qemu-arm] [PATCH] target-arm: Fix reset and migration of TTBCR(S) |
Date: |
Thu, 9 Jun 2016 19:09:54 +0300 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 |
On 09/06/16 19:03, Peter Maydell wrote:
> Commit 6459b94c26dd666badb3 broke reset and migration of the AArch32
> TTBCR(S) register if the guest used non-LPAE page tables. This is
> because the AArch32 TTBCR register definition is marked as ARM_CP_ALIAS,
> meaning that the AArch64 variant has to handle migration and reset.
> Although AArch64 TCR_EL3 doesn't need to care about the mask and
> base_mask fields, AArch32 may do so, and so we must use the special
> TTBCR reset and raw write functions to ensure they are set correctly.
>
> This doesn't affect TCR_EL2, because the AArch32 equivalent of that
> is HTCR, which never uses the non-LPAE page table variant.
>
> Signed-off-by: Peter Maydell <address@hidden>
> Reported-by: Pranith Kumar <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
> ---
> target-arm/helper.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 862e780..c9730d6 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -3765,8 +3765,11 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
> .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
> .access = PL3_RW,
> /* no .writefn needed as this can't cause an ASID change;
> - * no .raw_writefn or .resetfn needed as we never use mask/base_mask
> + * we must provide a .raw_writefn and .resetfn because we handle
> + * reset and migration for the AArch32 TTBCR(S), which might be
> + * using mask and base_mask.
> */
> + .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write,
> .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
> { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
> .type = ARM_CP_ALIAS,