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Re: [Qemu-arm] [Qemu-devel] [PATCH v5 9/9] tests: add a m25p80 test

From: Cédric Le Goater
Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH v5 9/9] tests: add a m25p80 test
Date: Mon, 4 Jul 2016 14:32:22 +0200
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Icedove/45.1.0

On 07/04/2016 02:11 PM, Peter Maydell wrote:
> On 4 July 2016 at 13:01, Cédric Le Goater <address@hidden> wrote:
>> On 07/04/2016 01:14 PM, Peter Maydell wrote:
>>> What is the test actually supposed to be doing?
>>> writel() says "write this 32 bit value as if the (guest) CPU
>>> wrote it to memory with a 32-bit write instruction".
>> The test (and the guest) is writing and reading data on the memory
>> region used by the SPI controller. This 'data' is then passed on
>> to the SPI flash module objects which expects BE order when there
>> are flash storage addresses are in the flow.
>> So I think the test needs to use mem{write,read} and not write*.
>> The result looks correct in the code. I will send a patchset
>> right after starting with this patch.
> If you were writing this test in a bit of native ARM code
> running in the guest, how would you write it?
> memread/memwrite are only the correct answer if you'd write
> the native arm code as something like
> memcpy(SPI_REGISTER, buf, len), which is not generally the
> way you talk to devices.

The SMC/SPI controller are driven by mmios and the flash module 
in a very similar way. The modules are mapped at some address, 
0x2000000 for the BMC, 0x3000000 for the host firmware. Writing 
to the mapped address triggers SPI transfers, you need to put the 
slave in user mode for that, by setting the appropriate registers 
in the controller. When not in that mode, you are in command mode, 
and in this case you access directly the contents of the flash.



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