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Re: [Qemu-arm] [PATCH 0/5] ast2400: some cleanups and a simple memory co

From: Peter Maydell
Subject: Re: [Qemu-arm] [PATCH 0/5] ast2400: some cleanups and a simple memory controller model
Date: Tue, 12 Jul 2016 18:10:28 +0100

On 12 July 2016 at 17:20, Cédric Le Goater <address@hidden> wrote:
> On 07/12/2016 04:19 PM, Peter Maydell wrote:
>> Hi; the release process is now at the point where I wouldn't really
>> want to put this into 2.7; I can be persuaded if you have a solid
>> justification, though.
> Here is my take to it  :
> * 1/5 hw/misc: fix typo in Aspeed SCU hw-strap2 property name
>   That's a minor fix
> * 2/5 ast2400: replace aspeed_smc_is_implemented()
>   That is not a fix but it removes some ugliness in the code, which
>   you had noticed, and which prevents us from fixing possible issues
>   nicely. So this is a preventive cleanup :)
> * 3/5 ast2400: pretend DMAs are done for U-boot
>   This is a work around fix. U-boot[1] uses DMAs to calibrate the
>   SPI flash module. It will spin until the DMA transfers are done.
> * 4/5 ast2400: externalize revision numbers
>   This is minor fix de-duplicating code and a prereq for the next
>   patch.
> * 5/5  ast2400: add a memory controller device model
>   That's an enhancement. It adds a basic device model for the memory
>   controller. This is needed by some version of the SDK relying on
>   the configuration register to know how much RAM the SOC has. Older
>   versions used a hardcoded value.
> The first patches should not be too much of a problem regarding the
> soft freeze. The last can wait 2.8 if you prefer, we need more work
> to fully support u-boot anyhow. I would be happy to have review
> though :) The model is very much like the SCU.

Thanks for the explanation. Patches 1-4 look straightforward
and I have put them in my target-arm.next tree. Since patch
5 isn't sufficient to get u-boot to work I think we should
defer it to 2.8. It is still on my to-review list.

-- PMM

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