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Re: [Qemu-arm] [PATCH 0/3] preliminaries for GICv3 virt support

From: Peter Maydell
Subject: Re: [Qemu-arm] [PATCH 0/3] preliminaries for GICv3 virt support
Date: Thu, 6 Oct 2016 18:48:09 +0100

On 6 October 2016 at 17:59, Edgar E. Iglesias <address@hidden> wrote:
> On Thu, Oct 06, 2016 at 02:21:04PM +0100, Peter Maydell wrote:
>> This set of three straightforward patches is a preliminary
>> for adding virtualization support to the GICv3 emulation:
>>  * add a (nop implementation of) MDCCINT_EL1, since KVM
>>    will read/write it on worldswitch
>>  * fix some bugs in the GICv3 trace events
>>  * add trace events for the generic timers
>>    (which I have been using for debugging)
>> I actually have almost all of the GICv3 virt code written,
>> but it currently has bugs which mean that a guest kernel
>> under KVM won't boot. Debugging in progress...
> That is very cool, we could soon enable EL2 :-)
> What kind of issues are you seeing?

The guest kernel just sits there like a lemon without printing
anything. Trying the kvm-unit-tests, the simple 'setup' test
works OK, but the one which tries to PSCI boot other SMP cores

> FWIW with our out of tree GICv2 virt models we've got issues
> with SMP Xen were things go nuts some times with virtual
> timer interrupts. Some times they take for ever to hit,
> like if we loose events.

Have you tried undoing the broken bit of virt.c that
marks the timer interrupts as edge triggered ?
(see 'hw/arm/virt: Don't incorrectly claim architectural timer
to be edge-triggered' in the branch below).

> Last time I looked at it, I noticed that our GICv2 virt
> implementation of the APR regs and EOIR stuff seems totally
> bogus (my bad).

Those were dodgy in original GICv2 for a long time...

https://git.linaro.org/people/peter.maydell/qemu-arm.git gicv3-virt
if you're interested in looking at my work-in-progress, though
as I say it is clearly badly broken right now.

-- PMM

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