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Re: [Qemu-arm] [PATCH v5 30/33] target-arm/cpu: don't reset TLB structur
Re: [Qemu-arm] [PATCH v5 30/33] target-arm/cpu: don't reset TLB structures, use cputlb to do it
Fri, 28 Oct 2016 10:17:08 +0100
mu4e 0.9.17; emacs 188.8.131.52
Peter Maydell <address@hidden> writes:
> On 28 October 2016 at 09:38, Alex Bennée <address@hidden> wrote:
>> Richard Henderson <address@hidden> writes:
>>> And don't we (or if not, shouldn't we)
>>> handle the tlb_flush generically for reset?
>> Probably. tlb_flush seems to be one of those things liberally sprinkled
>> in the arch code for all sorts of things but certainly cpu_reset is one
>> we could make the call from generic code.
> I think the theory I formed last time I looked at it is that
> if your CPU has no state which would require you to flush the
> TLB when it changes, then there's no need to flush the TLB
> on reset -- any entries still in the TLB from before reset are
> still valid after reset. For ARM a CPU reset will reset state
> like the ASID and the MMU-enabled bit which require a TLB flush
> on change, so we have to call tlb_flush here.
> You could argue that the set of CPUs which don't require a
> tlb flush on reset are not worth trying to optimise for
> like this and we should just do it generically.
Well it can't harm anyone. It would just mean all CPUs whatever their
semantics would have to re-fill the TLBs after a reset. I guess that
might be a concern for reset latency under TCG but I doubt anyone would