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[Qemu-arm] [PATCH 23/23] hw/arm/virt: Add board property to enable EL2
From: |
Peter Maydell |
Subject: |
[Qemu-arm] [PATCH 23/23] hw/arm/virt: Add board property to enable EL2 |
Date: |
Tue, 13 Dec 2016 10:36:24 +0000 |
Add a board level property to the virt board which will
enable EL2 on the CPU if the user asks for it. The
default is not to provide EL2. If EL2 is enabled then
we will use SMC as our PSCI conduit, and report the
virtualization support in the GICv3 device tree node.
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm/virt.c | 45 +++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 43 insertions(+), 2 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 5bde68c..7eec50a 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -78,6 +78,7 @@ typedef struct {
MachineState parent;
bool secure;
bool highmem;
+ bool virt;
int32_t gic_version;
struct arm_boot_info bootinfo;
const MemMapEntry *memmap;
@@ -480,6 +481,11 @@ static void fdt_add_gic_node(VirtMachineState *vms, int
type)
2, vms->memmap[VIRT_GIC_DIST].size,
2, vms->memmap[VIRT_GIC_REDIST].base,
2, vms->memmap[VIRT_GIC_REDIST].size);
+ if (vms->virt) {
+ qemu_fdt_setprop_cells(vms->fdt, "/intc", "interrupts",
+ GIC_FDT_IRQ_TYPE_PPI, ARCH_GICV3_MAINT_IRQ,
+ GIC_FDT_IRQ_FLAGS_LEVEL_HI);
+ }
} else {
/* 'cortex-a15-gic' means 'GIC v2' */
qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible",
@@ -1279,10 +1285,15 @@ static void machvirt_init(MachineState *machine)
* so it doesn't get in the way. Instead of starting secondary
* CPUs in PSCI powerdown state we will start them all running and
* let the boot ROM sort them out.
- * The usual case is that we do use QEMU's PSCI implementation.
+ * The usual case is that we do use QEMU's PSCI implementation;
+ * if the guest has EL2 then we will use SMC as the conduit,
+ * and otherwise we will use HVC (for backwards compatibility and
+ * because if we're using KVM then we must use HVC).
*/
if (vms->secure && firmware_loaded) {
vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
+ } else if (vms->virt) {
+ vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
} else {
vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
}
@@ -1312,6 +1323,12 @@ static void machvirt_init(MachineState *machine)
exit(1);
}
+ if (vms->virt && kvm_enabled()) {
+ error_report("mach-virt: KVM does not support providing "
+ "Virtualization extensions to the guest CPU");
+ exit(1);
+ }
+
if (vms->secure) {
if (kvm_enabled()) {
error_report("mach-virt: KVM does not support Security
extensions");
@@ -1368,7 +1385,7 @@ static void machvirt_init(MachineState *machine)
object_property_set_bool(cpuobj, false, "has_el3", NULL);
}
- if (object_property_find(cpuobj, "has_el2", NULL)) {
+ if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) {
object_property_set_bool(cpuobj, false, "has_el2", NULL);
}
@@ -1481,6 +1498,20 @@ static void virt_set_secure(Object *obj, bool value,
Error **errp)
vms->secure = value;
}
+static bool virt_get_virt(Object *obj, Error **errp)
+{
+ VirtMachineState *vms = VIRT_MACHINE(obj);
+
+ return vms->virt;
+}
+
+static void virt_set_virt(Object *obj, bool value, Error **errp)
+{
+ VirtMachineState *vms = VIRT_MACHINE(obj);
+
+ vms->virt = value;
+}
+
static bool virt_get_highmem(Object *obj, Error **errp)
{
VirtMachineState *vms = VIRT_MACHINE(obj);
@@ -1568,6 +1599,16 @@ static void virt_2_9_instance_init(Object *obj)
"Security Extensions (TrustZone)",
NULL);
+ /* EL2 is also disabled by default, for similar reasons */
+ vms->virt = false;
+ object_property_add_bool(obj, "virtualization", virt_get_virt,
+ virt_set_virt, NULL);
+ object_property_set_description(obj, "virtualization",
+ "Set on/off to enable/disable emulating a "
+ "guest CPU which implements the ARM "
+ "Virtualization Extensions",
+ NULL);
+
/* High memory is enabled by default */
vms->highmem = true;
object_property_add_bool(obj, "highmem", virt_get_highmem,
--
2.7.4
- [Qemu-arm] [PATCH 14/23] hw/intc/gicv3: Add data fields for virtualization support, (continued)
- [Qemu-arm] [PATCH 14/23] hw/intc/gicv3: Add data fields for virtualization support, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 19/23] hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update(), Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 16/23] hw/intc/arm_gicv3: Implement ICV_ registers which are just accessors, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 21/23] hw/arm/virt: Support using SMC for PSCI, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 13/23] hw/intc/gicv3: Add defines for ICH system register fields, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 15/23] hw/intc/arm_gicv3: Add accessors for ICH_ system registers, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 08/23] hw/intc/arm_gicv3: Add external IRQ lines for VIRQ and VFIQ, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 11/23] hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPU, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 23/23] hw/arm/virt: Add board property to enable EL2,
Peter Maydell <=
- [Qemu-arm] [PATCH 10/23] target-arm: Expose output GPIO line for VCPU maintenance interrupt, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 07/23] hw/arm/virt: Don't incorrectly claim architectural timer to be edge-triggered, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 04/23] hw/arm/virt: add 2.9 machine type, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 05/23] hw/arm/virt: Merge VirtBoardInfo and VirtMachineState, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 02/23] hw/intc/arm_gicv3: Remove incorrect usage of fieldoffset, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 09/23] hw/intc/arm_gic: Add external IRQ lines for VIRQ and VFIQ, Peter Maydell, 2016/12/13
- [Qemu-arm] [PATCH 06/23] hw/arm/virt: Rename 'vbi' variables to 'vms', Peter Maydell, 2016/12/13