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Re: [Qemu-arm] [RFC PATCH 0/4] FTGMAC100 model for the Aspeed SoCs

From: Peter Maydell
Subject: Re: [Qemu-arm] [RFC PATCH 0/4] FTGMAC100 model for the Aspeed SoCs
Date: Fri, 16 Dec 2016 16:48:57 +0000

On 29 November 2016 at 17:41, Cédric Le Goater <address@hidden> wrote:
> The Aspeed SoCs AST2400 and AST2500 have two FTGMAC100 ethernet
> controllers. This serie proposes a model for this device and a way to
> customize the bit definitions which are slightly different from the
> Faraday definitions.
> The last patch adds a fake NC-SI (Network Controller Sideband
> Interface) backend to pretend a NIC is being managed.

Could you explain in a bit more detail why the patchset is
marked "RFC" and what parts you want comments on? (An RFC
patchset that doesn't say this kind of thing in the cover letter
is dangerously close to being a "please ignore me" request :-))

-- PMM

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