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Re: [Qemu-arm] [RFC PATCH 0/4] FTGMAC100 model for the Aspeed SoCs

From: Cédric Le Goater
Subject: Re: [Qemu-arm] [RFC PATCH 0/4] FTGMAC100 model for the Aspeed SoCs
Date: Fri, 16 Dec 2016 18:24:08 +0100
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1

On 12/16/2016 05:48 PM, Peter Maydell wrote:
> On 29 November 2016 at 17:41, Cédric Le Goater <address@hidden> wrote:
>> The Aspeed SoCs AST2400 and AST2500 have two FTGMAC100 ethernet
>> controllers. This serie proposes a model for this device and a way to
>> customize the bit definitions which are slightly different from the
>> Faraday definitions.
>> The last patch adds a fake NC-SI (Network Controller Sideband
>> Interface) backend to pretend a NIC is being managed.
> Could you explain in a bit more detail why the patchset is
> marked "RFC" and what parts you want comments on?  (An RFC
> patchset that doesn't say this kind of thing in the cover letter
> is dangerously close to being a "please ignore me" request :-))

This is true. I didn't take the time to do so ...

Well, first, this is not an area I am familiar with, so this 
might look more like a draft for experts and the review should 
take that into account :) 

Also, I am not entirely satisfied with how the model looks for 
the first descriptor to transmit. May be I am trying to fit 
too well the driver.

And, the NC-SI is just a fake one to exercise the linux driver 
(we did find bugs with it) but I am wondering how far we should 
push the model. It's a rather complex interface.



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