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Re: [Qemu-arm] [PATCH 09/10] armv7m: FAULTMASK should be 0 on reset
From: |
Alex Bennée |
Subject: |
Re: [Qemu-arm] [PATCH 09/10] armv7m: FAULTMASK should be 0 on reset |
Date: |
Fri, 27 Jan 2017 13:56:59 +0000 |
User-agent: |
mu4e 0.9.19; emacs 25.1.91.4 |
Peter Maydell <address@hidden> writes:
> From: Michael Davidsaver <address@hidden>
>
> For M profile CPUs, FAULTMASK should be 0 on reset, like PRIMASK.
> QEMU stores FAULTMASK in the PSTATE F bit, so (as with PRIMASK in the
> I bit) we have to clear these to undo the A profile default of 1.
>
> Update the comment accordingly and move it so that it's closer to the
> code it's referring to.
>
> Signed-off-by: Michael Davidsaver <address@hidden>
> [PMM: rewrote commit message, moved comments]
> Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
> ---
> target/arm/cpu.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index c804f59..0814f73 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -179,15 +179,16 @@ static void arm_cpu_reset(CPUState *s)
> /* SVC mode with interrupts disabled. */
> env->uncached_cpsr = ARM_CPU_MODE_SVC;
> env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
> - /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
> - * clear at reset. Initial SP and PC are loaded from ROM.
> - */
> +
> if (arm_feature(env, ARM_FEATURE_M)) {
> uint32_t initial_msp; /* Loaded from 0x0 */
> uint32_t initial_pc; /* Loaded from 0x4 */
> uint8_t *rom;
>
> - env->daif &= ~PSTATE_I;
> + /* For M profile we store FAULTMASK and PRIMASK in the
> + * PSTATE F and I bits; these are both clear at reset.
> + */
> + env->daif &= ~(PSTATE_I | PSTATE_F);
>
> /* The reset value of this bit is IMPDEF, but ARM recommends
> * that it resets to 1, so QEMU always does that rather than making
> @@ -195,6 +196,7 @@ static void arm_cpu_reset(CPUState *s)
> */
> env->v7m.ccr = R_V7M_CCR_STKALIGN_MASK;
>
> + /* Load the initial SP and PC from the vector table at address 0 */
> rom = rom_ptr(0);
> if (rom) {
> /* Address zero is covered by ROM which hasn't yet been
--
Alex Bennée
- [Qemu-arm] [PATCH 00/10] More M profile bugfixes, Peter Maydell, 2017/01/24
- [Qemu-arm] [PATCH 01/10] target/arm: Drop IS_M() macro, Peter Maydell, 2017/01/24
- [Qemu-arm] [PATCH 07/10] armv7m: Report no-coprocessor faults correctly, Peter Maydell, 2017/01/24
- [Qemu-arm] [PATCH 09/10] armv7m: FAULTMASK should be 0 on reset, Peter Maydell, 2017/01/24
- Re: [Qemu-arm] [PATCH 09/10] armv7m: FAULTMASK should be 0 on reset,
Alex Bennée <=
- [Qemu-arm] [PATCH 08/10] armv7m: Honour CCR.USERSETMPEND, Peter Maydell, 2017/01/24
- [Qemu-arm] [PATCH 05/10] armv7m: honour CCR.STACKALIGN on exception entry, Peter Maydell, 2017/01/24
- [Qemu-arm] [PATCH 10/10] armv7m: R14 should reset to 0xffffffff, Peter Maydell, 2017/01/24
- [Qemu-arm] [PATCH 03/10] armv7m: add state for v7M CCR, CFSR, HFSR, DFSR, MMFAR, BFAR, Peter Maydell, 2017/01/24