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Re: [Qemu-arm] [PATCH 8/9] armv7m: Simpler and faster exception start
From: |
Alex Bennée |
Subject: |
Re: [Qemu-arm] [PATCH 8/9] armv7m: Simpler and faster exception start |
Date: |
Wed, 15 Feb 2017 14:18:05 +0000 |
User-agent: |
mu4e 0.9.19; emacs 25.2.3 |
Peter Maydell <address@hidden> writes:
> From: Michael Davidsaver <address@hidden>
>
> All the places in armv7m_cpu_do_interrupt() which pend an
> exception in the NVIC are doing so for synchronous
> exceptions. We know that we will always take some
> exception in this case, so we can just acknowledge it
> immediately, rather than returning and then immediately
> being called again because the NVIC has raised its outbound
> IRQ line.
>
> Signed-off-by: Michael Davidsaver <address@hidden>
> [PMM: tweaked commit message; added DEBUG to the set of
> exceptions we handle immediately, since it is synchronous
> when it results from the BKPT instruction]
> Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
> ---
> target/arm/helper.c | 15 +++++++++------
> 1 file changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 78bf9ab..8bdd99c 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -6071,22 +6071,22 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
> case EXCP_UDEF:
> armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
> env->v7m.cfsr |= R_V7M_CFSR_UNDEFINSTR_MASK;
> - return;
> + break;
> case EXCP_NOCP:
> armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
> env->v7m.cfsr |= R_V7M_CFSR_NOCP_MASK;
> - return;
> + break;
> case EXCP_SWI:
> /* The PC already points to the next instruction. */
> armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
> - return;
> + break;
> case EXCP_PREFETCH_ABORT:
> case EXCP_DATA_ABORT:
> /* TODO: if we implemented the MPU registers, this is where we
> * should set the MMFAR, etc from exception.fsr and
> exception.vaddress.
> */
> armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
> - return;
> + break;
> case EXCP_BKPT:
> if (semihosting_enabled()) {
> int nr;
> @@ -6101,9 +6101,8 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
> }
> }
> armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
> - return;
> + break;
> case EXCP_IRQ:
> - armv7m_nvic_acknowledge_irq(env->nvic);
> break;
> case EXCP_EXCEPTION_EXIT:
> do_v7m_exception_exit(env);
> @@ -6113,6 +6112,10 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
> return; /* Never happens. Keep compiler happy. */
> }
>
> + armv7m_nvic_acknowledge_irq(env->nvic);
> +
> + qemu_log_mask(CPU_LOG_INT, "... as %d\n", env->v7m.exception);
> +
> /* Align stack pointer if the guest wants that */
> if ((env->regs[13] & 4) && (env->v7m.ccr & R_V7M_CCR_STKALIGN_MASK)) {
> env->regs[13] -= 4;
--
Alex Bennée
- [Qemu-arm] [PATCH 0/9] Rewrite NVIC to not depend on the GIC, Peter Maydell, 2017/02/02
- [Qemu-arm] [PATCH 9/9] armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLE, Peter Maydell, 2017/02/02
- [Qemu-arm] [PATCH 8/9] armv7m: Simpler and faster exception start, Peter Maydell, 2017/02/02
- Re: [Qemu-arm] [PATCH 8/9] armv7m: Simpler and faster exception start,
Alex Bennée <=
- [Qemu-arm] [PATCH 7/9] armv7m: Remove unused armv7m_nvic_acknowledge_irq() return value, Peter Maydell, 2017/02/02
- [Qemu-arm] [PATCH 6/9] armv7m: Escalate exceptions to HardFault if necessary, Peter Maydell, 2017/02/02
- [Qemu-arm] [PATCH 4/9] armv7m: Fix condition check for taking exceptions, Peter Maydell, 2017/02/02
- [Qemu-arm] [PATCH 2/9] armv7m: Implement reading and writing of PRIGROUP, Peter Maydell, 2017/02/02
- [Qemu-arm] [PATCH 5/9] arm: gic: Remove references to NVIC, Peter Maydell, 2017/02/02