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[Qemu-arm] [PATCH v2 08/13] armv7m: Simpler and faster exception start
From: |
Peter Maydell |
Subject: |
[Qemu-arm] [PATCH v2 08/13] armv7m: Simpler and faster exception start |
Date: |
Thu, 16 Feb 2017 16:35:58 +0000 |
From: Michael Davidsaver <address@hidden>
All the places in armv7m_cpu_do_interrupt() which pend an
exception in the NVIC are doing so for synchronous
exceptions. We know that we will always take some
exception in this case, so we can just acknowledge it
immediately, rather than returning and then immediately
being called again because the NVIC has raised its outbound
IRQ line.
Signed-off-by: Michael Davidsaver <address@hidden>
[PMM: tweaked commit message; added DEBUG to the set of
exceptions we handle immediately, since it is synchronous
when it results from the BKPT instruction]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
---
target/arm/helper.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 050d8df..1844852 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6109,22 +6109,22 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
case EXCP_UDEF:
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
env->v7m.cfsr |= R_V7M_CFSR_UNDEFINSTR_MASK;
- return;
+ break;
case EXCP_NOCP:
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
env->v7m.cfsr |= R_V7M_CFSR_NOCP_MASK;
- return;
+ break;
case EXCP_SWI:
/* The PC already points to the next instruction. */
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
- return;
+ break;
case EXCP_PREFETCH_ABORT:
case EXCP_DATA_ABORT:
/* TODO: if we implemented the MPU registers, this is where we
* should set the MMFAR, etc from exception.fsr and exception.vaddress.
*/
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
- return;
+ break;
case EXCP_BKPT:
if (semihosting_enabled()) {
int nr;
@@ -6139,9 +6139,8 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
}
}
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
- return;
+ break;
case EXCP_IRQ:
- armv7m_nvic_acknowledge_irq(env->nvic);
break;
case EXCP_EXCEPTION_EXIT:
do_v7m_exception_exit(env);
@@ -6151,6 +6150,10 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
return; /* Never happens. Keep compiler happy. */
}
+ armv7m_nvic_acknowledge_irq(env->nvic);
+
+ qemu_log_mask(CPU_LOG_INT, "... as %d\n", env->v7m.exception);
+
/* Align stack pointer if the guest wants that */
if ((env->regs[13] & 4) && (env->v7m.ccr & R_V7M_CCR_STKALIGN_MASK)) {
env->regs[13] -= 4;
--
2.7.4
- [Qemu-arm] [PATCH v2 00/13] Rewrite NVIC to not depend on the GIC, Peter Maydell, 2017/02/16
- [Qemu-arm] [PATCH v2 02/13] armv7m: Implement reading and writing of PRIGROUP, Peter Maydell, 2017/02/16
- [Qemu-arm] [PATCH v2 13/13] armv7m: Allow SHCSR writes to change pending and active bits, Peter Maydell, 2017/02/16
- [Qemu-arm] [PATCH v2 12/13] armv7m: Raise correct kind of UsageFault for attempts to execute ARM code, Peter Maydell, 2017/02/16
- [Qemu-arm] [PATCH v2 11/13] armv7m: Check exception return consistency, Peter Maydell, 2017/02/16
- [Qemu-arm] [PATCH v2 10/13] armv7m: Extract "exception taken" code into functions, Peter Maydell, 2017/02/16
- [Qemu-arm] [PATCH v2 08/13] armv7m: Simpler and faster exception start,
Peter Maydell <=
- [Qemu-arm] [PATCH v2 09/13] armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLE, Peter Maydell, 2017/02/16
- [Qemu-arm] [PATCH v2 05/13] arm: gic: Remove references to NVIC, Peter Maydell, 2017/02/16
- [Qemu-arm] [PATCH v2 07/13] armv7m: Remove unused armv7m_nvic_acknowledge_irq() return value, Peter Maydell, 2017/02/16
- [Qemu-arm] [PATCH v2 04/13] armv7m: Fix condition check for taking exceptions, Peter Maydell, 2017/02/16
- [Qemu-arm] [PATCH v2 01/13] armv7m: Rename nvic_state to NVICState, Peter Maydell, 2017/02/16
- [Qemu-arm] [PATCH v2 06/13] armv7m: Escalate exceptions to HardFault if necessary, Peter Maydell, 2017/02/16
- [Qemu-arm] [PATCH v2 03/13] armv7m: Rewrite NVIC to not use any GIC code, Peter Maydell, 2017/02/16
- Re: [Qemu-arm] [PATCH v2 00/13] Rewrite NVIC to not depend on the GIC, Peter Maydell, 2017/02/16