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Re: [Qemu-arm] [PATCH v8 2/5] hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 reg
From: |
Vijay Kilari |
Subject: |
Re: [Qemu-arm] [PATCH v8 2/5] hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate |
Date: |
Wed, 22 Feb 2017 17:26:47 +0530 |
Hi Christoffer,
On Mon, Feb 20, 2017 at 3:21 PM, Peter Maydell <address@hidden> wrote:
> On 20 February 2017 at 06:21, Vijay Kilari <address@hidden> wrote:
>> Hi Peter,
>>
>> On Fri, Feb 17, 2017 at 7:25 PM, Peter Maydell <address@hidden> wrote:
> [on the guest-visible ICC_SRE_EL1 value]
>>> Is there a situation where KVM might allow a value other
>>> than 0x7?
>>
>> In KVM, the SRE_EL1 value is 0x1. During save, value
>> read from KVM is 0x1 though we reset to 0x7.
>
> 0x1 meanss "System Register Interface enabled, IRQ
> bypass enabled, FIQ bypass enabled". This seems
> rather a weird setting, because it means "the GICv3
> CPU interface functionality is disabled and the GICv3
> should signal interrupts via legacy IRQ and FIQ".
> Does KVM really support IRQ/FIQ bypass and does Linux
> really leave it enabled rather than turning it off
> by writing the value to 1?
>
> My expectation was that the KVM GICv3 emulation would
> make these bits RAO/WI like the TCG implementation.
> Is there maybe a bug in the kernel side where it
> doesn't implement bypass but has made these bits be
> RAZ/WI rather than RAO/WI ?
Do you have any inputs on this?
- [Qemu-arm] [PATCH v8 0/5] GICv3 live migration support, vijay . kilari, 2017/02/17
- [Qemu-arm] [PATCH v8 1/5] kernel: Add definitions for GICv3 attributes, vijay . kilari, 2017/02/17
- [Qemu-arm] [PATCH v8 2/5] hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate, vijay . kilari, 2017/02/17
- Re: [Qemu-arm] [PATCH v8 2/5] hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate, Auger Eric, 2017/02/17
- Re: [Qemu-arm] [PATCH v8 2/5] hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate, Peter Maydell, 2017/02/17
- Re: [Qemu-arm] [PATCH v8 2/5] hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate, Vijay Kilari, 2017/02/20
- Re: [Qemu-arm] [PATCH v8 2/5] hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate, Peter Maydell, 2017/02/20
- Re: [Qemu-arm] [PATCH v8 2/5] hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate,
Vijay Kilari <=
- Re: [Qemu-arm] [PATCH v8 2/5] hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate, Peter Maydell, 2017/02/22
- Re: [Qemu-arm] [PATCH v8 2/5] hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate, Marc Zyngier, 2017/02/22
- Re: [Qemu-arm] [PATCH v8 2/5] hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate, Peter Maydell, 2017/02/22
[Qemu-arm] [PATCH v8 3/5] hw/intc/arm_gicv3_kvm: Implement get/put functions, vijay . kilari, 2017/02/17
[Qemu-arm] [PATCH v8 4/5] target-arm: Add GICv3CPUState in CPUARMState struct, vijay . kilari, 2017/02/17
[Qemu-arm] [PATCH v8 5/5] hw/intc/arm_gicv3_kvm: Reset GICv3 cpu interface registers, vijay . kilari, 2017/02/17