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[Qemu-arm] [RFC PATCH 5/9] arm/cpu.h: align VFP registers
From: |
Alex Bennée |
Subject: |
[Qemu-arm] [RFC PATCH 5/9] arm/cpu.h: align VFP registers |
Date: |
Thu, 17 Aug 2017 19:04:00 +0100 |
Signed-off-by: Alex Bennée <address@hidden>
---
target/arm/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index b39d64aa0b..cdd47cb868 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -457,8 +457,8 @@ typedef struct CPUARMState {
* the two execution states, and means we do not need to explicitly
* map these registers when changing states.
*/
- float64 regs[64];
-
+ float64 regs[64] __attribute__((aligned(16)));
+ /* VFP system registers */
uint32_t xregs[16];
/* We store these fpcsr fields separately for convenience. */
int vec_len;
--
2.13.0
- [Qemu-arm] [RFC PATCH 0/9] TCG Vector types and example conversion, Alex Bennée, 2017/08/17
- [Qemu-arm] [RFC PATCH 3/9] tcg: generate ptrs to vector registers, Alex Bennée, 2017/08/17
- [Qemu-arm] [RFC PATCH 5/9] arm/cpu.h: align VFP registers,
Alex Bennée <=
- [Qemu-arm] [RFC PATCH 4/9] helper-head: add support for vec type, Alex Bennée, 2017/08/17
- [Qemu-arm] [RFC PATCH 2/9] tcg: introduce the concepts of a TCGv_vec register type, Alex Bennée, 2017/08/17
- [Qemu-arm] [RFC PATCH 1/9] tcg/README: listify the TCG types., Alex Bennée, 2017/08/17
- [Qemu-arm] [RFC PATCH 9/9] target/arm/translate-a64: vectorise smull vD.4s, vN.[48]s, vM.h[], Alex Bennée, 2017/08/17
- [Qemu-arm] [RFC PATCH 7/9] target/arm/translate-a64: register global vectors, Alex Bennée, 2017/08/17
- [Qemu-arm] [RFC PATCH 6/9] target/arm/translate-a64: regnames -> x_regnames, Alex Bennée, 2017/08/17