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Re: [Qemu-arm] [Qemu-devel] [PATCH 03/20] target/arm: Prepare for CONTRO
From: |
Richard Henderson |
Subject: |
Re: [Qemu-arm] [Qemu-devel] [PATCH 03/20] target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode |
Date: |
Thu, 5 Oct 2017 12:09:23 -0400 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 |
On 09/22/2017 10:59 AM, Peter Maydell wrote:
> In the v7M architecture, there is an invariant that if the CPU is
> in Handler mode then the CONTROL.SPSEL bit cannot be nonzero.
> This in turn means that the current stack pointer is always
> indicated by CONTROL.SPSEL, even though Handler mode always uses
> the Main stack pointer.
>
> In v8M, this invariant is removed, and CONTROL.SPSEL may now
> be nonzero in Handler mode (though Handler mode still always
> uses the Main stack pointer). In preparation for this change,
> change how we handle this bit: rename switch_v7m_sp() to
> the now more accurate write_v7m_control_spsel(), and make it
> check both the handler mode state and the SPSEL bit.
>
> Note that this implicitly changes the point at which we switch
> active SP on exception exit from before we pop the exception
> frame to after it.
>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> target/arm/cpu.h | 8 ++++++-
> hw/intc/armv7m_nvic.c | 2 +-
> target/arm/helper.c | 65
> ++++++++++++++++++++++++++++++++++-----------------
> 3 files changed, 51 insertions(+), 24 deletions(-)
Reviewed-by: Richard Henderson <address@hidden>
r~
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