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Re: [Qemu-arm] [RISU PATCH 00/10] Initial support for SVE
From: |
Alex Bennée |
Subject: |
Re: [Qemu-arm] [RISU PATCH 00/10] Initial support for SVE |
Date: |
Wed, 08 Nov 2017 11:02:15 +0000 |
User-agent: |
mu4e 1.0-alpha0; emacs 26.0.90 |
Dave Martin <address@hidden> writes:
> On Tue, Nov 07, 2017 at 03:05:48PM +0000, Alex Bennée wrote:
>> Hi,
>>
>> These patches apply on-top of the last clean-up series:
>>
>> Subject: [RISU PATCH 0/7] Add @Group support and some aarch64.risu cleanups
>> Date: Tue, 31 Oct 2017 14:54:37 +0000
>> Message-Id: <address@hidden>
>>
>> This series adds support for SVE to RISU. Most of the initial patches
>> are plumbing changes to better support arch specific option flags
>> (cleaning up a TODO in the process). I also needed to ensure configure
>> actually honoured CPPFLAGS so it could be passed yet to be released
>> headers.
>
> Should there be a getauxval(AT_HWCAP) & HWCAP_SVE check in this series
> somewhere?
>
> I don't know enough about how RISU is structured to know whether/where
> this is needed.
That would be a saner runtime check to do but it's a balance as RISU is
a fairly specialist tool which kind of assumes people know what they are
doing.
The current check is on SVE_MAGIC in the header files which does mean a
binary compiled on an SVE headered system is now carrying about a much
larger register dump even when run without the --test-sve flag.
Whether it makes sense to be more flexible is a call I'll leave up to
Peter.
>
> [...]
>
> Cheers
> ---Dave
--
Alex Bennée
- Re: [Qemu-arm] [RISU PATCH 06/10] configure: support CPPFLAGS, (continued)