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Re: [Qemu-arm] [PATCH v3 11/30] sdhci: Add i.MX specific subtype of SDHC
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From: |
Peter Maydell |
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Subject: |
Re: [Qemu-arm] [PATCH v3 11/30] sdhci: Add i.MX specific subtype of SDHCI |
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Date: |
Thu, 23 Nov 2017 09:52:24 +0000 |
On 22 November 2017 at 20:43, Andrey Smirnov <address@hidden> wrote:
> On Tue, Nov 21, 2017 at 10:02 AM, Peter Maydell
> <address@hidden> wrote:
>> On 6 November 2017 at 15:47, Andrey Smirnov <address@hidden> wrote:
>>> +/* Controller does not provide transfer-complete interrupt when not busy */
>>> +#define SDHCI_QUIRK_NO_BUSY_IRQ BIT(14)
>>
>> We only have one quirk, so why is it bit 14?
>>
>
> I took that code from Linux kernel, so I tried to keep it as is (same
> with unsigned long in quirks field).
That's fine, but if so we should have a comment that that's what we're
doing, so that subsequent additions by other contributors follow the
same convention.
thanks
-- PMM
- [Qemu-arm] [PATCH v3 07/30] imx_fec: Add support for multiple Tx DMA rings, (continued)
- [Qemu-arm] [PATCH v3 09/30] imx_fec: Fix a typo in imx_enet_receive(), Andrey Smirnov, 2017/11/06
- [Qemu-arm] [PATCH v3 12/30] sdhci: Implement write method of ACMD12ERRSTS register, Andrey Smirnov, 2017/11/06
- [Qemu-arm] [PATCH v3 14/30] i.MX: Add code to emulate i.MX2 watchdog IP block, Andrey Smirnov, 2017/11/06
- [Qemu-arm] [PATCH v3 13/30] i.MX: Add code to emulate i.MX7 CCM, PMU and ANALOG IP blocks, Andrey Smirnov, 2017/11/06