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Re: [Qemu-arm] [PATCH 0/2] GICv2 & GICv3: RAZ/WI reserved addresses rath
Re: [Qemu-arm] [PATCH 0/2] GICv2 & GICv3: RAZ/WI reserved addresses rather than aborting
Tue, 9 Jan 2018 16:58:56 +0100
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On 01/09/18 15:24, Peter Maydell wrote:
> Ping for code review?
> -- PMM
> On 13 December 2017 at 16:52, Peter Maydell <address@hidden> wrote:
>> The GICv2 and GICv3 specifications
here's where I had started running from your patch...
>> say that reserved register
>> addresses should RAZ/WI.
...and I remarked only looking over my shoulder that "RAZ/WI" is not a
Sorry, no clue about any of this -- where should I read up?
Ard did ask a question though:
CC'ing Drew, Eric and Wei. In particular (IIUC) Eric has been looking
into a weird "why do we have so many (and so slow) aborts with GICv4
emulation" issue, at launching UEFI.
>> This means we need to return MEMTX_OK, not
>> MEMTX_ERROR, because now that we support generating external aborts
>> the latter will cause an abort on new board models.
>> In particular, at least some versions of UEFI try to
>> access a reserved address in the GICv3 redistributor
>> (at SGI_base + 0x184) and fail to boot on the virt board
>> without this.
>> -- PMM
>> Peter Maydell (2):
>> hw/intc/arm_gicv3: Make reserved register addresses RAZ/WI
>> hw/intc/arm_gic: reserved register addresses are RAZ/WI
>> hw/intc/arm_gic.c | 5 +++--
>> hw/intc/arm_gicv3_dist.c | 13 +++++++++++++
>> hw/intc/arm_gicv3_its_common.c | 8 +++-----
>> hw/intc/arm_gicv3_redist.c | 13 +++++++++++++
>> 4 files changed, 32 insertions(+), 7 deletions(-)