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Re: [Qemu-arm] [PATCH v2 10/11] target/arm: Decode aa32 armv8.3 3-same
From: |
Peter Maydell |
Subject: |
Re: [Qemu-arm] [PATCH v2 10/11] target/arm: Decode aa32 armv8.3 3-same |
Date: |
Mon, 15 Jan 2018 18:49:36 +0000 |
On 18 December 2017 at 17:24, Richard Henderson
<address@hidden> wrote:
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> target/arm/translate.c | 65
> ++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 65 insertions(+)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 1a0b0eaced..e57844c019 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -7662,6 +7662,65 @@ static int disas_neon_data_insn(DisasContext *s,
> uint32_t insn)
> return 0;
> }
>
> +/* ARMv8.3 reclaims a portion of the LDC2/STC2 coprocessor 8 space. */
> +
> +static int disas_neon_insn_cp8_3same(DisasContext *s, uint32_t insn)
> +{
> + void (*fn_gvec_ptr)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
> + int rd, rn, rm, rot, size, opr_sz;
> + TCGv_ptr fpst;
> + bool q;
> +
> + /* FIXME: this access check should not take precedence over UNDEF
> + * for invalid encodings; we will generate incorrect syndrome information
> + * for attempts to execute invalid vfp/neon encodings with FP disabled.
> + */
(Forgot this bit before hitting send on the other email...)
Unlike the sprawling disas_vfp_insn(), we're in a position to get the
order of checks right here. Just move it and the vfp_enabled test a
bit further down...
> + if (s->fp_excp_el) {
> + gen_exception_insn(s, 4, EXCP_UDEF,
> + syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
> + return 0;
> + }
> + if (!s->vfp_enabled) {
> + return 1;
> + }
> + if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA)) {
> + return 1;
> + }
> +
> + q = extract32(insn, 6, 1);
> + size = extract32(insn, 20, 1);
> + VFP_DREG_D(rd, insn);
> + VFP_DREG_N(rn, insn);
> + VFP_DREG_M(rm, insn);
> + if ((rd | rn | rm) & q) {
> + return 1;
> + }
> +
> + if (extract32(insn, 21, 1)) {
> + /* VCMLA */
> + rot = extract32(insn, 23, 2);
> + fn_gvec_ptr = size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah;
> + } else if (extract32(insn, 23, 1)) {
> + /* VCADD */
> + rot = extract32(insn, 24, 1);
> + fn_gvec_ptr = size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh;
> + } else {
> + /* Assuming the register fields remain, only bit 24 remains
> undecoded:
> + * 1111_110x_0d0s_nnnn_dddd_1000_nqm0_mmmm
> + */
> + return 1;
> + }
...to here.
> +
> + opr_sz = (1 + q) * 8;
> + fpst = get_fpstatus_ptr(1);
> + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd),
> + vfp_reg_offset(1, rn),
> + vfp_reg_offset(1, rm), fpst,
> + opr_sz, opr_sz, rot, fn_gvec_ptr);
> + tcg_temp_free_ptr(fpst);
> + return 0;
> +}
> +
thanks
-- PMM