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Re: [Qemu-arm] [Qemu-devel] [PATCH v2 32/32] arm/translate-a64: add all
From: |
Richard Henderson |
Subject: |
Re: [Qemu-arm] [Qemu-devel] [PATCH v2 32/32] arm/translate-a64: add all single op FP16 to handle_fp_1src_half |
Date: |
Fri, 9 Feb 2018 10:37:59 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 |
On 02/08/2018 09:31 AM, Alex Bennée wrote:
> This includes FMOV, FABS, FNEG, FSQRT and FRINT[NPMZAXI]. We re-use
> existing helpers to achieve this.
>
> Signed-off-by: Alex Bennée <address@hidden>
> ---
> target/arm/translate-a64.c | 72
> ++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 72 insertions(+)
>
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index 92adf43a89..265bfb14d0 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -4508,6 +4508,66 @@ static void disas_fp_csel(DisasContext *s, uint32_t
> insn)
> tcg_temp_free_i64(t_true);
> }
>
> +/* Floating-point data-processing (1 source) - half precision */
> +static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
> +{
> + TCGv_ptr fpst = NULL;
> + TCGv_i32 tcg_op;
> + TCGv_i32 tcg_res;
> +
> + tcg_op = read_fp_sreg(s, rn);
> + tcg_res = tcg_temp_new_i32();
> +
> + switch (opcode) {
> + case 0x0: /* FMOV */
> + tcg_gen_mov_i32(tcg_res, tcg_op);
> + break;
> + case 0x1: /* FABS */
> + gen_helper_advsimd_absh(tcg_res, tcg_op);
> + break;
> + case 0x2: /* FNEG */
> + tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
> + break;
> + case 0x3: /* FSQRT */
> + gen_helper_sqrt_f16(tcg_res, tcg_op, cpu_env);
> + break;
> + case 0x8: /* FRINTN */
> + case 0x9: /* FRINTP */
> + case 0xa: /* FRINTM */
> + case 0xb: /* FRINTZ */
> + case 0xc: /* FRINTA */
> + {
> + TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
> + fpst = get_fpstatus_ptr(true);
> +
> + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
> + gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
> +
> + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
> + tcg_temp_free_i32(tcg_rmode);
> + break;
> + }
> + case 0xe: /* FRINTX */
> + fpst = get_fpstatus_ptr(true);
> + gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, fpst);
> + break;
> + case 0xf: /* FRINTI */
> + fpst = get_fpstatus_ptr(true);
> + gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
> + break;
> + default:
> + abort();
> + }
> +
> + write_fp_sreg(s, rd, tcg_res);
Some of these helpers will zero-extend from 16 bits, but at least a few won't
-- notably fmov and fneg. I wonder if it wouldn't be best to have a
write_fp_hreg.
r~
- Re: [Qemu-arm] [Qemu-devel] [PATCH v2 31/32] arm/translate-a64: implement simd_scalar_three_reg_same_fp16, (continued)
- [Qemu-arm] [PATCH v2 19/32] arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16, Alex Bennée, 2018/02/08
- [Qemu-arm] [PATCH v2 17/32] arm/translate-a64: initial decode for simd_two_reg_misc_fp16, Alex Bennée, 2018/02/08
- [Qemu-arm] [PATCH v2 21/32] arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16, Alex Bennée, 2018/02/08
- [Qemu-arm] [PATCH v2 18/32] arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16, Alex Bennée, 2018/02/08
- [Qemu-arm] [PATCH v2 32/32] arm/translate-a64: add all single op FP16 to handle_fp_1src_half, Alex Bennée, 2018/02/08
- Re: [Qemu-arm] [Qemu-devel] [PATCH v2 32/32] arm/translate-a64: add all single op FP16 to handle_fp_1src_half,
Richard Henderson <=
- [Qemu-arm] [PATCH v2 22/32] arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16, Alex Bennée, 2018/02/08
- [Qemu-arm] [PATCH v2 27/32] arm/helper.c: re-factor rsqrte and add rsqrte_f16, Alex Bennée, 2018/02/08
- [Qemu-arm] [PATCH v2 30/32] arm/translate-a64: add all FP16 ops in simd_scalar_pairwise, Alex Bennée, 2018/02/08
- [Qemu-arm] [PATCH v2 15/32] arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed, Alex Bennée, 2018/02/08
- [Qemu-arm] [PATCH v2 28/32] arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16, Alex Bennée, 2018/02/08