Re: [Qemu-arm] [PATCH v2 04/67] target/arm: Implement SVE Bitwise Logical - Unpredicated Group

[Richard Henderson]

On 02/22/2018 10:04 AM, Peter Maydell wrote:
> On 17 February 2018 at 18:22, Richard Henderson
> <address@hidden> wrote:
>> These were the instructions that were stubbed out when
>> introducing the decode skeleton.
>>
>> Signed-off-by: Richard Henderson <address@hidden>
>> ---
>>  target/arm/translate-sve.c | 50 
>> +++++++++++++++++++++++++++++++++++++++-------
>>  1 file changed, 43 insertions(+), 7 deletions(-)
>>
>> diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
>> index 2c9e4733cb..50cf2a1fdd 100644
>> --- a/target/arm/translate-sve.c
>> +++ b/target/arm/translate-sve.c
>> @@ -32,6 +32,10 @@
>>  #include "trace-tcg.h"
>>  #include "translate-a64.h"
>>
>> +typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
>> +typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
>> +                        uint32_t, uint32_t, uint32_t);
> 
> I see we already have these in translate-a64.c -- put them in
> translate-a64.h ?

Good plan, thanks.


r~