[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-arm] [PATCH v4 12/21] target/arm: Make PMOVSCLR and PMUSERENR 64 b
From: |
Aaron Lindsay |
Subject: |
[Qemu-arm] [PATCH v4 12/21] target/arm: Make PMOVSCLR and PMUSERENR 64 bits wide |
Date: |
Tue, 17 Apr 2018 16:37:56 -0400 |
This is a bug fix to ensure 64-bit reads of these registers don't read
adjacent data.
Signed-off-by: Aaron Lindsay <address@hidden>
---
target/arm/cpu.h | 4 ++--
target/arm/helper.c | 5 +++--
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a56e9a0..9f769ae 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -367,8 +367,8 @@ typedef struct CPUARMState {
uint32_t c9_data;
uint64_t c9_pmcr; /* performance monitor control register */
uint64_t c9_pmcnten; /* perf monitor counter enables */
- uint32_t c9_pmovsr; /* perf monitor overflow status */
- uint32_t c9_pmuserenr; /* perf monitor user enable */
+ uint64_t c9_pmovsr; /* perf monitor overflow status */
+ uint64_t c9_pmuserenr; /* perf monitor user enable */
uint64_t c9_pmselr; /* perf monitor counter selection register */
uint64_t c9_pminten; /* perf monitor interrupt enables */
union { /* Memory attribute redirection */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 62cace7..20b42b4 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1427,7 +1427,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
.writefn = pmcntenclr_write },
{ .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
- .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
+ .access = PL0_RW,
+ .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
.accessfn = pmreg_access,
.writefn = pmovsr_write,
.raw_writefn = raw_write },
@@ -1487,7 +1488,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.accessfn = pmreg_access_xevcntr },
{ .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
.access = PL0_R | PL1_RW, .accessfn = access_tpm,
- .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
+ .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmuserenr),
.resetvalue = 0,
.writefn = pmuserenr_write, .raw_writefn = raw_write },
{ .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64,
--
Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
- [Qemu-arm] [PATCH v4 05/21] target/arm: Fetch GICv3 state directly from CPUARMState, (continued)
- [Qemu-arm] [PATCH v4 05/21] target/arm: Fetch GICv3 state directly from CPUARMState, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 04/21] target/arm: Mask PMU register writes based on PMCR_EL0.N, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 03/21] target/arm: Reorganize PMCCNTR accesses, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 06/21] target/arm: Support multiple EL change hooks, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 07/21] target/arm: Add pre-EL change hooks, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 08/21] target/arm: Allow EL change hooks to do IO, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 09/21] target/arm: Fix bitmask for PMCCFILTR writes, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 11/21] target/arm: Allow AArch32 access for PMCCFILTR, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 12/21] target/arm: Make PMOVSCLR and PMUSERENR 64 bits wide,
Aaron Lindsay <=
- [Qemu-arm] [PATCH v4 10/21] target/arm: Filter cycle counter based on PMCCFILTR_EL0, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 14/21] target/arm: Implement PMOVSSET, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 18/21] target/arm: PMU: Set PMCR.N to 4, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 13/21] target/arm: Add ARM_FEATURE_V7VE for v7 Virtualization Extensions, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 17/21] target/arm: PMU: Add instruction and cycle events, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 15/21] target/arm: Add array for supported PMU events, generate PMCEID[01], Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 16/21] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 19/21] target/arm: Implement PMSWINC, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 20/21] target/arm: Mark PMINTENSET accesses as possibly doing IO, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 21/21] target/arm: Send interrupts on PMU counter overflow, Aaron Lindsay, 2018/04/17