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[Qemu-arm] [PATCH v2 05/14] target/arm: Implement FMOV (general) for fp1
From: |
Richard Henderson |
Subject: |
[Qemu-arm] [PATCH v2 05/14] target/arm: Implement FMOV (general) for fp16 |
Date: |
Wed, 2 May 2018 15:15:43 -0700 |
Adding the fp16 moves to/from general registers.
Cc: address@hidden
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-a64.c | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index c64c3ed99d..247a4f0cce 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -5463,6 +5463,15 @@ static void handle_fmov(DisasContext *s, int rd, int rn,
int type, bool itof)
tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
clear_vec_high(s, true, rd);
break;
+ case 3:
+ /* 16 bit */
+ tmp = tcg_temp_new_i64();
+ tcg_gen_ext16u_i64(tmp, tcg_rn);
+ write_fp_dreg(s, rd, tmp);
+ tcg_temp_free_i64(tmp);
+ break;
+ default:
+ g_assert_not_reached();
}
} else {
TCGv_i64 tcg_rd = cpu_reg(s, rd);
@@ -5480,6 +5489,12 @@ static void handle_fmov(DisasContext *s, int rd, int rn,
int type, bool itof)
/* 64 bits from top half */
tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn));
break;
+ case 3:
+ /* 16 bit */
+ tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16));
+ break;
+ default:
+ g_assert_not_reached();
}
}
}
@@ -5519,10 +5534,15 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t
insn)
case 0xa: /* 64 bit */
case 0xd: /* 64 bit to top half of quad */
break;
+ case 0x6: /* 16-bit */
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+ break;
+ }
+ /* fallthru */
default:
/* all other sf/type/rmode combinations are invalid */
unallocated_encoding(s);
- break;
+ return;
}
if (!fp_access_check(s)) {
--
2.14.3
- [Qemu-arm] [PATCH v2 00/14] target/arm: Fixups for ARM_FEATURE_V8_FP16, Richard Henderson, 2018/05/02
- [Qemu-arm] [PATCH v2 01/14] target/arm: Implement vector shifted SCVF/UCVF for fp16, Richard Henderson, 2018/05/02
- [Qemu-arm] [PATCH v2 02/14] target/arm: Implement vector shifted FCVT for fp16, Richard Henderson, 2018/05/02
- [Qemu-arm] [PATCH v2 04/14] target/arm: Clear SVE high bits for FMOV, Richard Henderson, 2018/05/02
- [Qemu-arm] [PATCH v2 03/14] target/arm: Fix float16 to/from int16, Richard Henderson, 2018/05/02
- [Qemu-arm] [PATCH v2 05/14] target/arm: Implement FMOV (general) for fp16,
Richard Henderson <=
- [Qemu-arm] [PATCH v2 06/14] target/arm: Implement FCVT (scalar, integer) for fp16, Richard Henderson, 2018/05/02
- [Qemu-arm] [PATCH v2 07/14] target/arm: Implement FCVT (scalar, fixed-point) for fp16, Richard Henderson, 2018/05/02
- [Qemu-arm] [PATCH v2 09/14] target/arm: Implement FP data-processing (2 source) for fp16, Richard Henderson, 2018/05/02
- [Qemu-arm] [PATCH v2 14/14] target/arm: Fix sqrt_f16 exception raising, Richard Henderson, 2018/05/02
- [Qemu-arm] [PATCH v2 12/14] target/arm: Implement FCSEL for fp16, Richard Henderson, 2018/05/02
- [Qemu-arm] [PATCH v2 10/14] target/arm: Implement FP data-processing (3 source) for fp16, Richard Henderson, 2018/05/02
- [Qemu-arm] [PATCH v2 08/14] target/arm: Introduce and use read_fp_hreg, Richard Henderson, 2018/05/02