Hello,
I'm working on a body of code that relies heavily on the MPU faulting mechanism on cortex-m processors. This makes debugging other aspects difficult as GDB often traps in MPU fault while single stepping.
On a real target it appears I can mask this by setting bit 4 of DEMCR (Debug Exception and Monitor Control Register). This looks to be unimplemented in QEMU. Does anyone have any ideas/guidance of where I should start looking to add support or another mechanism for disabling GDB trapping this ISR vector?
Thanks,
Elliot
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Founder
Tiny Labs - Small Space Big Ideas