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[Qemu-arm] [PATCH 5/5] target/arm: Treat SCTLR_EL1.M as if it were zero
From: |
Peter Maydell |
Subject: |
[Qemu-arm] [PATCH 5/5] target/arm: Treat SCTLR_EL1.M as if it were zero when HCR_EL2.TGE is set |
Date: |
Tue, 24 Jul 2018 12:59:50 +0100 |
One of the required effects of setting HCR_EL2.TGE is that when
SCR_EL3.NS is 1 then SCTLR_EL1.M must behave as if it is zero for
all purposes except direct reads. That is, it effectively disables
the MMU for the NS EL0/EL1 translation regime.
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 699189ebd7b..efd258fdb59 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8402,6 +8402,14 @@ static inline bool
regime_translation_disabled(CPUARMState *env,
if (mmu_idx == ARMMMUIdx_S2NS) {
return (env->cp15.hcr_el2 & HCR_VM) == 0;
}
+
+ if (env->cp15.hcr_el2 & HCR_TGE) {
+ /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
+ if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) == 1) {
+ return true;
+ }
+ }
+
return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
}
--
2.17.1
- [Qemu-arm] [PATCH 0/5] target/arm: Implement HCR_EL2.TGE ("trap general exceptions"), Peter Maydell, 2018/07/24
- [Qemu-arm] [PATCH 3/5] target/arm: Honour HCR_EL2.TGE when raising synchronous exceptions, Peter Maydell, 2018/07/24
- [Qemu-arm] [PATCH 5/5] target/arm: Treat SCTLR_EL1.M as if it were zero when HCR_EL2.TGE is set,
Peter Maydell <=
- [Qemu-arm] [PATCH 1/5] target/arm: Mask virtual interrupts if HCR_EL2.TGE is set, Peter Maydell, 2018/07/24
- [Qemu-arm] [PATCH 2/5] target/arm: Honour HCR_EL2.TGE and MDCR_EL2.TDE in debug register access checks, Peter Maydell, 2018/07/24
- [Qemu-arm] [PATCH 4/5] target/arm: Provide accessor functions for HCR_EL2.{IMO, FMO, AMO}, Peter Maydell, 2018/07/24