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Re: [Qemu-arm] [PATCH 07/10] target/arm: Implement ESR_EL2/HSR for AArch
From: |
Edgar E. Iglesias |
Subject: |
Re: [Qemu-arm] [PATCH 07/10] target/arm: Implement ESR_EL2/HSR for AArch32 and no-EL2 |
Date: |
Tue, 14 Aug 2018 16:59:56 +0200 |
User-agent: |
NeoMutt/20170609 (1.8.3) |
On Tue, Aug 14, 2018 at 01:42:51PM +0100, Peter Maydell wrote:
> The AArch32 HSR is the equivalent of AArch64 ESR_EL2;
> we can implement it by marking our existing ESR_EL2 regdef
> as STATE_BOTH. It also needs to be "RES0 from EL3 if
> EL2 not implemented", so add the missing stanza to
> el3_no_el2_cp_reginfo.
Reviewed-by: Edgar E. Iglesias <address@hidden>
>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> target/arm/helper.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index d6e98e9d606..80855302089 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -3763,6 +3763,10 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
> .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
> .access = PL2_RW,
> .type = ARM_CP_CONST, .resetvalue = 0 },
> + { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
> + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
> + .access = PL2_RW,
> + .type = ARM_CP_CONST, .resetvalue = 0 },
> { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
> .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
> .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> @@ -3926,7 +3930,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
> .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
> .access = PL2_RW,
> .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
> - { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
> + { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
> .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
> .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2])
> },
> { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
> --
> 2.18.0
>
- [Qemu-arm] [PATCH 00/10] target/arm: Some pieces of support for 32-bit Hyp mode, Peter Maydell, 2018/08/14
- [Qemu-arm] [PATCH 06/10] target/arm: Implement AArch32 Hyp FARs, Peter Maydell, 2018/08/14
- [Qemu-arm] [PATCH 07/10] target/arm: Implement ESR_EL2/HSR for AArch32 and no-EL2, Peter Maydell, 2018/08/14
- [Qemu-arm] [PATCH 08/10] target/arm: Permit accesses to ELR_Hyp from Hyp mode via MSR/MRS (banked), Peter Maydell, 2018/08/14
- [Qemu-arm] [PATCH 03/10] target/arm: Implement RAZ/WI HACTLR2, Peter Maydell, 2018/08/14
- [Qemu-arm] [PATCH 01/10] target/arm: Correct typo in HAMAIR1 regdef name, Peter Maydell, 2018/08/14