Re: [Qemu-arm] [PATCH v4 5/6] loader: Implement .hex file loader

[Philippe Mathieu-Daudé]

On 08/13/2018 12:56 PM, Stefan Hajnoczi wrote:
> On Fri, Aug 10, 2018 at 02:00:44AM -0300, Philippe Mathieu-Daudé wrote:
>> On 08/03/2018 11:47 AM, Stefan Hajnoczi wrote:
>>> +        parser->rom_start_address = parser->next_address_to_write;
>>> +        parser->current_rom_index = 0;
>>> +        break;
>>> +
>>> +    case START_SEG_ADDR_RECORD:
>>> +        if (line->byte_count != 4 && line->address != 0) {
>>> +            return -1;
>>> +        }
>>> +
>>> +        /* x86 16-bit CS:IP segmented addressing */
>>> +        *(parser->start_addr) = (((line->data[0] << 8) | line->data[1]) << 
>>> 4) |
>>> +                                (line->data[2] << 8) | line->data[3];
>>
>> Can you add a qtest for this case?
>> For the HEX loader I understand the specs as this is the same parsing as
>> the START_LINEAR_ADDR_RECORD case; so I disagree with data[0] and
>> data[1] shifts.
> 
> x86 real-mode CS:IP addressing means (CS << 4) + IP.  It produces 24-bit
> addresses on 80286 and later.  This is not the same as
> START_LINEAR_ADDR_RECORD.

OK!

> 
> GNU bfd implements it as follows:
> 
>   abfd->start_address += (HEX4 (buf) << 4) + HEX4 (buf + 4);

Hmm any idea why they use +4 ?

> 
> https://sourceware.org/git/?p=binutils.git;a=blob;f=bfd/ihex.c;h=09f756a1c2c11e57c5da15a6ff96491275575b86;hb=HEAD#l415
> 
> Thanks for commenting on this, I had written (CS << 4) | IP instead of
> (CS << 4) + IP.  This will be fixed in the next revision.
> 
>> This is different for the consumer (i386 expects 2 16-bit registers but
>> HexParser->start_addr is a hwaddr, used as a single (at least) 32-bit
>> register.
> 
> I think you're saying that on x86 the guest CS:IP registers should be
> set.  This loader is never called from hw/i386/ so it doesn't matter at
> this time.

OK.

> 
> GNU bfd uses START_SEG_ADDR_RECORD records on non-x86 architectures
> where there are no segment registers and that's where we've encountered
> them.
>

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