Re: [Qemu-arm] [PATCH] imx_spi: Unset XCH when TX FIFO becomes empty

[Peter Maydell]

On 31 July 2018 at 21:10, Trent Piepho via Qemu-arm <address@hidden> wrote:
> The current emulation will clear the XCH bit when a burst finishes.
> This is not quite correct.  According to the i.MX7d referemce manual,
> Rev 0.1, §10.1.7.3:
>
>     This bit [XCH] is cleared automatically when all data in the TXFIFO
>     and the shift register has been shifted out.
>
> So XCH should be cleared when the FIFO empties, not on completion of a
> burst.  The FIFO is 64 x 32 bits = 2048 bits, while the max burst size
> is larger at 4096 bits.  So it's possible that the burst is not finished
> after the TXFIFO empties.
>
> Sending a large block (> 2048 bits) with the Linux driver will use a
> burst that is larger than the TXFIFO.  After the TXFIFO has emptied XCH
> does not become unset, as the burst is not yet finished.
>
> What should happen after the TXFIFO empties is the driver will refill it
> and set XCH.  The rising edge of XCH will trigger another transfer to
> begin.  However, since the emulation does not set XCH to 0, there is no
> rising edge and the next trasfer never begins.
>
> Signed-off-by: Trent Piepho <address@hidden>

Applied to target-arm.next. Thanks for the detailed commit message,
it made the patch much easier to review.

-- PMM