Re: [Qemu-arm] [Qemu-devel] [PATCH 19/22] hw/ssi/pl022: Correct wrong value for PL022_INT_RT

[Richard Henderson]

On 08/20/2018 07:11 AM, Peter Maydell wrote:
> The PL022 interrupt registers have bits allocated as:
>  0: ROR (receive overrun)
>  1: RT (receive timeout)
>  2: RX (receive FIFO half full or less)
>  3: TX (transmit FIFO half full or less)
> 
> A cut and paste error meant we had the wrong value for
> the PL022_INT_RT constant. This bug doesn't affect device
> behaviour, because we don't implmenet the receive timeout

implement.

> feature and so never set that interrupt bit.
> 
> Signed-off-by: Peter Maydell <address@hidden>
> ---
>  hw/ssi/pl022.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Richard Henderson <address@hidden>


r~