Re: [Qemu-arm] [PATCH v6 00/14] More fully implement ARM PMUv3

[Peter Maydell]

On 10 October 2018 at 21:37, Aaron Lindsay <address@hidden> wrote:
> The ARM PMU implementation currently contains a basic cycle counter, but
> it is often useful to gather counts of other events, filter them based
> on execution mode, and/or be notified on counter overflow. These patches
> flesh out the implementations of various PMU registers including
> PM[X]EVCNTR and PM[X]EVTYPER, add a struct definition to represent
> arbitrary counter types, implement mode filtering, send interrupts on
> counter overflow, and add instruction, cycle, and software increment
> events.
>
> Since v5 [1] I have:
> * Taken a first pass at addressing migration
> * Restructured the list of supported events, and ensured they're all
>   initialized
> * Fixed aliasing for PMOVSSET
> * Added ARM_CP_IO for PMINTENCLR and PMINTENCLR_EL1
> * Addressed a few non-code issues (comment style, patch staging,
>   spelling, etc.)
>
> [1] - https://lists.gnu.org/archive/html/qemu-devel/2018-06/msg06830.html
>
> Aaron Lindsay (14):
>   target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly
>     doing IO
>   target/arm: Mask PMOVSR writes based on supported counters

Hi; Richard has reviewed most of this series and suggested some
changes (thanks!); I'll just take these first two patches into
target-arm.next, since they're simple fixes that have been reviewed.

thanks
-- PMM