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Re: [Qemu-arm] [PATCH] accel/tcg/user-exec: Don't parse aarch64 insns to
Re: [Qemu-arm] [PATCH] accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write
Sun, 20 Jan 2019 07:38:18 +1100
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0
On 1/9/19 5:00 AM, Peter Maydell wrote:
> In cpu_signal_handler() for aarch64 hosts, currently we parse
> the faulting instruction to see if it is a load or a store.
> Since the 3.16 kernel (~2014), the kernel has provided us with
> the syndrome register for a fault, which includes the WnR bit.
> Use this instead if it is present, only falling back to
> instruction parsing if not.
> Signed-off-by: Peter Maydell <address@hidden>
> Since I originally asked the kernel folks to add the ESR context
> so we could use it in QEMU, I figured that it was about time
> (five years later...) to write the code to make use of it.
> I wanted to say "everybody surely has at least a 3.16
> kernel for aarch64 machines" and delete the fallback code,
> but it turns out that the gcc compile farm box has 3.13.0...
> accel/tcg/user-exec.c | 66 ++++++++++++++++++++++++++++++++++---------
> 1 file changed, 52 insertions(+), 14 deletions(-)
Reviewed-by: Richard Henderson <address@hidden>
I should note that we fail to generate esr_context from aarch64-linux-user.