Re: [Qemu-arm] [PATCH] Check access permission to ADDVL/ADDPL/RDVL

[Peter Maydell]

Richard, Amir -- it looks like you both sent exactly the
same patch at pretty much exactly the same time. Any
preferences for whose version I apply ? :-)

thanks
-- PMM

On Thu, 14 Mar 2019 at 16:41, Amir Charif <address@hidden> wrote:
>
> These instructions do not trap when SVE is disabled in EL0,
> causing them to be executed with wrong size information.
>
> Signed-off-by: Amir Charif <address@hidden>
> ---
>  target/arm/translate-sve.c | 22 ++++++++++++++--------
>  1 file changed, 14 insertions(+), 8 deletions(-)
>
> diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
> index 3a2eb51..245cd82 100644
> --- a/target/arm/translate-sve.c
> +++ b/target/arm/translate-sve.c
> @@ -943,24 +943,30 @@ static bool trans_INDEX_rr(DisasContext *s, 
> arg_INDEX_rr *a)
>
>  static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a)
>  {
> -    TCGv_i64 rd = cpu_reg_sp(s, a->rd);
> -    TCGv_i64 rn = cpu_reg_sp(s, a->rn);
> -    tcg_gen_addi_i64(rd, rn, a->imm * vec_full_reg_size(s));
> +    if (sve_access_check(s)) {
> +        TCGv_i64 rd = cpu_reg_sp(s, a->rd);
> +        TCGv_i64 rn = cpu_reg_sp(s, a->rn);
> +        tcg_gen_addi_i64(rd, rn, a->imm * vec_full_reg_size(s));
> +    }
>      return true;
>  }
>
>  static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a)
>  {
> -    TCGv_i64 rd = cpu_reg_sp(s, a->rd);
> -    TCGv_i64 rn = cpu_reg_sp(s, a->rn);
> -    tcg_gen_addi_i64(rd, rn, a->imm * pred_full_reg_size(s));
> +    if (sve_access_check(s)) {
> +        TCGv_i64 rd = cpu_reg_sp(s, a->rd);
> +        TCGv_i64 rn = cpu_reg_sp(s, a->rn);
> +        tcg_gen_addi_i64(rd, rn, a->imm * pred_full_reg_size(s));
> +    }
>      return true;
>  }
>
>  static bool trans_RDVL(DisasContext *s, arg_RDVL *a)
>  {
> -    TCGv_i64 reg = cpu_reg(s, a->rd);
> -    tcg_gen_movi_i64(reg, a->imm * vec_full_reg_size(s));
> +    if (sve_access_check(s)) {
> +        TCGv_i64 reg = cpu_reg(s, a->rd);
> +        tcg_gen_movi_i64(reg, a->imm * vec_full_reg_size(s));
> +    }
>      return true;
>  }
>
> --
> 2.7.4