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[Qemu-arm] [PATCH 02/26] hw/intc/armv7m_nvic: Allow reading of M-profile
From: |
Peter Maydell |
Subject: |
[Qemu-arm] [PATCH 02/26] hw/intc/armv7m_nvic: Allow reading of M-profile MVFR* registers |
Date: |
Tue, 16 Apr 2019 13:57:20 +0100 |
For M-profile the MVFR* ID registers are memory mapped, in the
range we implement via the NVIC. Allow them to be read.
(If the CPU has no FPU, these registers are defined to be RAZ.)
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/armv7m_nvic.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index ab822f42514..45d72f86bdf 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1222,6 +1222,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t
offset, MemTxAttrs attrs)
return 0;
}
return cpu->env.v7m.sfar;
+ case 0xf40: /* MVFR0 */
+ return cpu->isar.mvfr0;
+ case 0xf44: /* MVFR1 */
+ return cpu->isar.mvfr1;
+ case 0xf48: /* MVFR2 */
+ return cpu->isar.mvfr2;
default:
bad_offset:
qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset);
--
2.20.1
- [Qemu-arm] [PATCH 00/26] target/arm: Implement M profile floating point, Peter Maydell, 2019/04/16
- [Qemu-arm] [PATCH 01/26] target/arm: Make sure M-profile FPSCR RES0 bits are not settable, Peter Maydell, 2019/04/16
- [Qemu-arm] [PATCH 02/26] hw/intc/armv7m_nvic: Allow reading of M-profile MVFR* registers,
Peter Maydell <=
- [Qemu-arm] [PATCH 03/26] target/arm: Implement dummy versions of M-profile FP-related registers, Peter Maydell, 2019/04/16
- [Qemu-arm] [PATCH 04/26] target/arm: Disable most VFP sysregs for M-profile, Peter Maydell, 2019/04/16
- [Qemu-arm] [PATCH 06/26] target/arm: Decode FP instructions for M profile, Peter Maydell, 2019/04/16
- [Qemu-arm] [PATCH 07/26] target/arm: Clear CONTROL_S.SFPA in SG insn if FPU present, Peter Maydell, 2019/04/16
- [Qemu-arm] [PATCH 08/26] target/arm: Handle SFPA and FPCA bits in reads and writes of CONTROL, Peter Maydell, 2019/04/16