[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-arm] [PATCH v2 07/42] target/arm: Convert VMINNM, VMAXNM to decode
From: |
Peter Maydell |
Subject: |
[Qemu-arm] [PATCH v2 07/42] target/arm: Convert VMINNM, VMAXNM to decodetree |
Date: |
Tue, 11 Jun 2019 11:53:16 +0100 |
Convert the VMINNM and VMAXNM instructions to decodetree.
As with VSEL, we leave the trans_VMINMAXNM() function
in translate.c for the moment.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/arm/translate.c | 41 ++++++++++++++++++++++++------------
target/arm/vfp-uncond.decode | 5 +++++
2 files changed, 33 insertions(+), 13 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 6ee60303eeb..53badde1f52 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -3202,11 +3202,31 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
return true;
}
-static int handle_vminmaxnm(uint32_t insn, uint32_t rd, uint32_t rn,
- uint32_t rm, uint32_t dp)
+static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)
{
- uint32_t vmin = extract32(insn, 6, 1);
- TCGv_ptr fpst = get_fpstatus_ptr(0);
+ uint32_t rd, rn, rm;
+ bool dp = a->dp;
+ bool vmin = a->op;
+ TCGv_ptr fpst;
+
+ if (!dc_isar_feature(aa32_vminmaxnm, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (dp && !dc_isar_feature(aa32_fp_d32, s) &&
+ ((a->vm | a->vn | a->vd) & 0x10)) {
+ return false;
+ }
+ rd = a->vd;
+ rn = a->vn;
+ rm = a->vm;
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ fpst = get_fpstatus_ptr(0);
if (dp) {
TCGv_i64 frn, frm, dest;
@@ -3247,7 +3267,7 @@ static int handle_vminmaxnm(uint32_t insn, uint32_t rd,
uint32_t rn,
}
tcg_temp_free_ptr(fpst);
- return 0;
+ return true;
}
static int handle_vrint(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
@@ -3359,23 +3379,18 @@ static const uint8_t fp_decode_rm[] = {
static int disas_vfp_misc_insn(DisasContext *s, uint32_t insn)
{
- uint32_t rd, rn, rm, dp = extract32(insn, 8, 1);
+ uint32_t rd, rm, dp = extract32(insn, 8, 1);
if (dp) {
VFP_DREG_D(rd, insn);
- VFP_DREG_N(rn, insn);
VFP_DREG_M(rm, insn);
} else {
rd = VFP_SREG_D(insn);
- rn = VFP_SREG_N(insn);
rm = VFP_SREG_M(insn);
}
- if ((insn & 0x0fb00e10) == 0x0e800a00 &&
- dc_isar_feature(aa32_vminmaxnm, s)) {
- return handle_vminmaxnm(insn, rd, rn, rm, dp);
- } else if ((insn & 0x0fbc0ed0) == 0x0eb80a40 &&
- dc_isar_feature(aa32_vrint, s)) {
+ if ((insn & 0x0fbc0ed0) == 0x0eb80a40 &&
+ dc_isar_feature(aa32_vrint, s)) {
/* VRINTA, VRINTN, VRINTP, VRINTM */
int rounding = fp_decode_rm[extract32(insn, 16, 2)];
return handle_vrint(insn, rd, rm, dp, rounding);
diff --git a/target/arm/vfp-uncond.decode b/target/arm/vfp-uncond.decode
index b7f7c27fe86..8ab201fa058 100644
--- a/target/arm/vfp-uncond.decode
+++ b/target/arm/vfp-uncond.decode
@@ -45,3 +45,8 @@ VSEL 1111 1110 0. cc:2 .... .... 1010 .0.0 .... \
vm=%vm_sp vn=%vn_sp vd=%vd_sp dp=0
VSEL 1111 1110 0. cc:2 .... .... 1011 .0.0 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp dp=1
+
+VMINMAXNM 1111 1110 1.00 .... .... 1010 . op:1 .0 .... \
+ vm=%vm_sp vn=%vn_sp vd=%vd_sp dp=0
+VMINMAXNM 1111 1110 1.00 .... .... 1011 . op:1 .0 .... \
+ vm=%vm_dp vn=%vn_dp vd=%vd_dp dp=1
--
2.20.1
- [Qemu-arm] [PATCH v2 04/42] target/arm: Fix Cortex-R5F MVFR values, (continued)
- [Qemu-arm] [PATCH v2 04/42] target/arm: Fix Cortex-R5F MVFR values, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 02/42] target/arm: Add stubs for AArch32 VFP decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 03/42] target/arm: Factor out VFP access checking code, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 09/42] target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 06/42] target/arm: Convert the VSEL instructions to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 14/42] target/arm: Convert VFP two-register transfer insns to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 05/42] target/arm: Explicitly enable VFP short-vectors for aarch32 -cpu max, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 11/42] target/arm: Add helpers for VFP register loads and stores, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 13/42] target/arm: Convert "single-precision" register moves to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 12/42] target/arm: Convert "double-precision" register moves to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 07/42] target/arm: Convert VMINNM, VMAXNM to decodetree,
Peter Maydell <=
- [Qemu-arm] [PATCH v2 01/42] decodetree: Fix comparison of Field, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 08/42] target/arm: Convert VRINTA/VRINTN/VRINTP/VRINTM to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 15/42] target/arm: Convert VFP VLDR and VSTR to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 17/42] target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 10/42] target/arm: Move the VFP trans_* functions to translate-vfp.inc.c, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 22/42] target/arm: Convert VMUL to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 16/42] target/arm: Convert the VFP load/store multiple insns to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 24/42] target/arm: Convert VADD to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 21/42] target/arm: Convert VFP VNMLA to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 18/42] target/arm: Convert VFP VMLA to decodetree, Peter Maydell, 2019/06/11