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[Qemu-arm] [PATCH 3/7] target/arm: Remove redundant shift tests
From: |
Richard Henderson |
Subject: |
[Qemu-arm] [PATCH 3/7] target/arm: Remove redundant shift tests |
Date: |
Thu, 8 Aug 2019 13:26:12 -0700 |
The immediate shift generator functions already test for,
and eliminate, the case of a shift by zero.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate.c | 19 +++++++------------
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 94170af134..3ddc404b3b 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8826,8 +8826,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int
insn)
shift = (insn >> 10) & 3;
/* ??? In many cases it's not necessary to do a
rotate, a shift is sufficient. */
- if (shift != 0)
- tcg_gen_rotri_i32(tmp, tmp, shift * 8);
+ tcg_gen_rotri_i32(tmp, tmp, shift * 8);
op1 = (insn >> 20) & 7;
switch (op1) {
case 0: gen_sxtb16(tmp); break;
@@ -9904,8 +9903,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t
insn)
shift = (insn >> 4) & 3;
/* ??? In many cases it's not necessary to do a
rotate, a shift is sufficient. */
- if (shift != 0)
- tcg_gen_rotri_i32(tmp, tmp, shift * 8);
+ tcg_gen_rotri_i32(tmp, tmp, shift * 8);
op = (insn >> 20) & 7;
switch (op) {
case 0: gen_sxth(tmp); break;
@@ -10632,11 +10630,10 @@ static void disas_thumb2_insn(DisasContext *s,
uint32_t insn)
case 7:
goto illegal_op;
default: /* Saturate. */
- if (shift) {
- if (op & 1)
- tcg_gen_sari_i32(tmp, tmp, shift);
- else
- tcg_gen_shli_i32(tmp, tmp, shift);
+ if (op & 1) {
+ tcg_gen_sari_i32(tmp, tmp, shift);
+ } else {
+ tcg_gen_shli_i32(tmp, tmp, shift);
}
tmp2 = tcg_const_i32(imm);
if (op & 4) {
@@ -10827,9 +10824,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t
insn)
goto illegal_op;
}
tmp = load_reg(s, rm);
- if (shift) {
- tcg_gen_shli_i32(tmp, tmp, shift);
- }
+ tcg_gen_shli_i32(tmp, tmp, shift);
tcg_gen_add_i32(addr, addr, tmp);
tcg_temp_free_i32(tmp);
break;
--
2.17.1
- [Qemu-arm] [PATCH 0/7] target/arm: Misc cleanups, Richard Henderson, 2019/08/08
- [Qemu-arm] [PATCH 1/7] target/arm: Use tcg_gen_extract_i32 for shifter_out_im, Richard Henderson, 2019/08/08
- [Qemu-arm] [PATCH 2/7] target/arm: Use tcg_gen_deposit_i32 for PKHBT, PKHTB, Richard Henderson, 2019/08/08
- [Qemu-arm] [PATCH 3/7] target/arm: Remove redundant shift tests,
Richard Henderson <=
- [Qemu-arm] [PATCH 4/7] target/arm: Use ror32 instead of open-coding the operation, Richard Henderson, 2019/08/08
- [Qemu-arm] [PATCH 5/7] target/arm: Use tcg_gen_rotri_i32 for gen_swap_half, Richard Henderson, 2019/08/08
- [Qemu-arm] [PATCH 6/7] target/arm: Simplify SMMLA, SMMLAR, SMMLS, SMMLSR, Richard Henderson, 2019/08/08
- [Qemu-arm] [PATCH 7/7] target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word, Richard Henderson, 2019/08/08
- Re: [Qemu-arm] [PATCH 0/7] target/arm: Misc cleanups, Peter Maydell, 2019/08/15