[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-arm] [PATCH v4 38/69] target/arm: Convert PLI, PLD, PLDW
From: |
Richard Henderson |
Subject: |
[Qemu-arm] [PATCH v4 38/69] target/arm: Convert PLI, PLD, PLDW |
Date: |
Wed, 4 Sep 2019 12:30:28 -0700 |
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate.c | 37 +++++++++++++++++++-----------------
target/arm/a32-uncond.decode | 10 ++++++++++
2 files changed, 30 insertions(+), 17 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index a599da96e1..3f02532d12 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10252,6 +10252,26 @@ static bool trans_SETEND(DisasContext *s, arg_SETEND
*a)
return true;
}
+/*
+ * Preload instructions
+ * All are nops, contingent on the appropriate arch level.
+ */
+
+static bool trans_PLD(DisasContext *s, arg_PLD *a)
+{
+ return ENABLE_ARCH_5TE;
+}
+
+static bool trans_PLDW(DisasContext *s, arg_PLD *a)
+{
+ return arm_dc_feature(s, ARM_FEATURE_V7MP);
+}
+
+static bool trans_PLI(DisasContext *s, arg_PLD *a)
+{
+ return ENABLE_ARCH_7;
+}
+
/*
* Legacy decoder.
*/
@@ -10312,23 +10332,6 @@ static void disas_arm_insn(DisasContext *s, unsigned
int insn)
}
return;
}
- if (((insn & 0x0f30f000) == 0x0510f000) ||
- ((insn & 0x0f30f010) == 0x0710f000)) {
- if ((insn & (1 << 22)) == 0) {
- /* PLDW; v7MP */
- if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) {
- goto illegal_op;
- }
- }
- /* Otherwise PLD; v5TE+ */
- ARCH(5TE);
- return;
- }
- if (((insn & 0x0f70f000) == 0x0450f000) ||
- ((insn & 0x0f70f010) == 0x0650f000)) {
- ARCH(7);
- return; /* PLI; V7 */
- }
if (((insn & 0x0f700000) == 0x04100000) ||
((insn & 0x0f700010) == 0x06100000)) {
if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) {
diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode
index 32253b4f9a..ddc5edfa5e 100644
--- a/target/arm/a32-uncond.decode
+++ b/target/arm/a32-uncond.decode
@@ -54,3 +54,13 @@ SB 1111 0101 0111 1111 1111 0000 0111 0000
# Set Endianness
SETEND 1111 0001 0000 0001 0000 00 E:1 0 0000 0000 &setend
+
+# Preload instructions
+
+PLD 1111 0101 -101 ---- 1111 ---- ---- ---- # (imm, lit) 5te
+PLDW 1111 0101 -001 ---- 1111 ---- ---- ---- # (imm, lit) 7mp
+PLI 1111 0100 -101 ---- 1111 ---- ---- ---- # (imm, lit) 7
+
+PLD 1111 0111 -101 ---- 1111 ----- -- 0 ---- # (register) 5te
+PLDW 1111 0111 -001 ---- 1111 ----- -- 0 ---- # (register) 7mp
+PLI 1111 0110 -101 ---- 1111 ----- -- 0 ---- # (register) 7
--
2.17.1
- [Qemu-arm] [PATCH v4 30/69] target/arm: Diagnose too few registers in list for LDM/STM, (continued)
- [Qemu-arm] [PATCH v4 30/69] target/arm: Diagnose too few registers in list for LDM/STM, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 33/69] target/arm: Convert SVC, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 26/69] target/arm: Convert Signed multiply, signed and unsigned divide, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 28/69] target/arm: Convert LDM, STM, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 25/69] target/arm: Convert packing, unpacking, saturation, and reversal, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 32/69] target/arm: Convert B, BL, BLX (immediate), Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 35/69] target/arm: Convert Clear-Exclusive, Barriers, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 34/69] target/arm: Convert RFE and SRS, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 39/69] target/arm: Convert Unallocated memory hint, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 37/69] target/arm: Convert SETEND, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 38/69] target/arm: Convert PLI, PLD, PLDW,
Richard Henderson <=
- [Qemu-arm] [PATCH v4 36/69] target/arm: Convert CPS (privileged), Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 41/69] target/arm: Convert SG, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 40/69] target/arm: Convert Table Branch, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 42/69] target/arm: Convert TT, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 44/69] target/arm: Simplify disas_arm_insn, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 43/69] target/arm: Simplify disas_thumb2_insn, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 45/69] target/arm: Add skeleton for T16 decodetree, Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 46/69] target/arm: Convert T16 data-processing (two low regs), Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 47/69] target/arm: Convert T16 load/store (register offset), Richard Henderson, 2019/09/04
- [Qemu-arm] [PATCH v4 48/69] target/arm: Convert T16 load/store (immediate offset), Richard Henderson, 2019/09/04