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[PATCH v5 07/22] target/arm: Implement ADDG, SUBG instructions
From: |
Richard Henderson |
Subject: |
[PATCH v5 07/22] target/arm: Implement ADDG, SUBG instructions |
Date: |
Fri, 11 Oct 2019 09:47:29 -0400 |
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
v2: Shift offset in translate; use extract32.
---
target/arm/helper-a64.h | 2 ++
target/arm/internals.h | 4 +++
target/arm/mte_helper.c | 32 +++++++++++++++++
target/arm/translate-a64.c | 71 ++++++++++++++++++++++++++------------
4 files changed, 86 insertions(+), 23 deletions(-)
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index 6ff7f5b756..268c114b79 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -107,3 +107,5 @@ DEF_HELPER_FLAGS_2(mte_check1, TCG_CALL_NO_WG, i64, env,
i64)
DEF_HELPER_FLAGS_2(mte_check2, TCG_CALL_NO_WG, i64, env, i64)
DEF_HELPER_FLAGS_3(mte_check3, TCG_CALL_NO_WG, i64, env, i64, i32)
DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64)
+DEF_HELPER_FLAGS_4(addg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32)
+DEF_HELPER_FLAGS_4(subg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index bfa243be06..a434743b15 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1085,4 +1085,8 @@ void arm_log_exception(int idx);
*/
#define GMID_EL1_BS 6
+/* We associate one allocation tag per 16 bytes, the minimum. */
+#define LOG2_TAG_GRANULE 4
+#define TAG_GRANULE (1 << LOG2_TAG_GRANULE)
+
#endif
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
index 9848849a91..c3edc51bba 100644
--- a/target/arm/mte_helper.c
+++ b/target/arm/mte_helper.c
@@ -222,3 +222,35 @@ uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn,
uint64_t rm)
return address_with_allocation_tag(rn, rtag);
}
+
+uint64_t HELPER(addg)(CPUARMState *env, uint64_t ptr,
+ uint32_t offset, uint32_t tag_offset)
+{
+ int el = arm_current_el(env);
+ uint64_t sctlr = arm_sctlr(env, el);
+ int rtag = 0;
+
+ if (allocation_tag_access_enabled(env, el, sctlr)) {
+ int start_tag = allocation_tag_from_addr(ptr);
+ uint16_t exclude = extract32(env->cp15.gcr_el1, 0, 16);
+ rtag = choose_nonexcluded_tag(start_tag, tag_offset, exclude);
+ }
+
+ return address_with_allocation_tag(ptr + offset, rtag);
+}
+
+uint64_t HELPER(subg)(CPUARMState *env, uint64_t ptr,
+ uint32_t offset, uint32_t tag_offset)
+{
+ int el = arm_current_el(env);
+ uint64_t sctlr = arm_sctlr(env, el);
+ int rtag = 0;
+
+ if (allocation_tag_access_enabled(env, el, sctlr)) {
+ int start_tag = allocation_tag_from_addr(ptr);
+ uint16_t exclude = extract32(env->cp15.gcr_el1, 0, 16);
+ rtag = choose_nonexcluded_tag(start_tag, tag_offset, exclude);
+ }
+
+ return address_with_allocation_tag(ptr - offset, rtag);
+}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 83d253d67f..26aee0c1c9 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -3628,7 +3628,9 @@ static void disas_pc_rel_adr(DisasContext *s, uint32_t
insn)
* sf: 0 -> 32bit, 1 -> 64bit
* op: 0 -> add , 1 -> sub
* S: 1 -> set flags
- * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
+ * shift: 00 -> LSL imm by 0,
+ * 01 -> LSL imm by 12
+ * 10 -> ADDG, SUBG
*/
static void disas_add_sub_imm(DisasContext *s, uint32_t insn)
{
@@ -3639,10 +3641,10 @@ static void disas_add_sub_imm(DisasContext *s, uint32_t
insn)
bool setflags = extract32(insn, 29, 1);
bool sub_op = extract32(insn, 30, 1);
bool is_64bit = extract32(insn, 31, 1);
+ bool is_tag = false;
TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd);
- TCGv_i64 tcg_result;
switch (shift) {
case 0x0:
@@ -3650,35 +3652,58 @@ static void disas_add_sub_imm(DisasContext *s, uint32_t
insn)
case 0x1:
imm <<= 12;
break;
+ case 0x2:
+ /* ADDG, SUBG */
+ if (!is_64bit || setflags || (imm & 0x30) ||
+ !dc_isar_feature(aa64_mte_insn_reg, s)) {
+ goto do_unallocated;
+ }
+ is_tag = true;
+ break;
default:
+ do_unallocated:
unallocated_encoding(s);
return;
}
- tcg_result = tcg_temp_new_i64();
- if (!setflags) {
- if (sub_op) {
- tcg_gen_subi_i64(tcg_result, tcg_rn, imm);
- } else {
- tcg_gen_addi_i64(tcg_result, tcg_rn, imm);
- }
- } else {
- TCGv_i64 tcg_imm = tcg_const_i64(imm);
- if (sub_op) {
- gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm);
- } else {
- gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm);
- }
- tcg_temp_free_i64(tcg_imm);
- }
+ if (is_tag) {
+ TCGv_i32 tag_offset = tcg_const_i32(imm & 15);
+ TCGv_i32 offset = tcg_const_i32((imm >> 6) << LOG2_TAG_GRANULE);
- if (is_64bit) {
- tcg_gen_mov_i64(tcg_rd, tcg_result);
+ if (sub_op) {
+ gen_helper_subg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset);
+ } else {
+ gen_helper_addg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset);
+ }
+ tcg_temp_free_i32(tag_offset);
+ tcg_temp_free_i32(offset);
} else {
- tcg_gen_ext32u_i64(tcg_rd, tcg_result);
- }
+ TCGv_i64 tcg_result;
- tcg_temp_free_i64(tcg_result);
+ if (!setflags) {
+ tcg_result = tcg_rd;
+ if (sub_op) {
+ tcg_gen_subi_i64(tcg_result, tcg_rn, imm);
+ } else {
+ tcg_gen_addi_i64(tcg_result, tcg_rn, imm);
+ }
+ } else {
+ TCGv_i64 tcg_imm = tcg_const_i64(imm);
+ tcg_result = new_tmp_a64(s);
+ if (sub_op) {
+ gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm);
+ } else {
+ gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm);
+ }
+ tcg_temp_free_i64(tcg_imm);
+ }
+
+ if (is_64bit) {
+ tcg_gen_mov_i64(tcg_rd, tcg_result);
+ } else {
+ tcg_gen_ext32u_i64(tcg_rd, tcg_result);
+ }
+ }
}
/* The input should be a value in the bottom e bits (with higher
--
2.17.1
- [PATCH v5 00/22] target/arm: Implement ARMv8.5-MemTag, system mode, Richard Henderson, 2019/10/11
- [PATCH v5 01/22] target/arm: Add MTE_ACTIVE to tb_flags, Richard Henderson, 2019/10/11
- [PATCH v5 02/22] target/arm: Add regime_has_2_ranges, Richard Henderson, 2019/10/11
- [PATCH v5 03/22] target/arm: Add MTE system registers, Richard Henderson, 2019/10/11
- [PATCH v5 04/22] target/arm: Add helper_mte_check{1,2,3}, Richard Henderson, 2019/10/11
- [PATCH v5 05/22] target/arm: Suppress tag check for sp+offset, Richard Henderson, 2019/10/11
- [PATCH v5 06/22] target/arm: Implement the IRG instruction, Richard Henderson, 2019/10/11
- [PATCH v5 07/22] target/arm: Implement ADDG, SUBG instructions,
Richard Henderson <=
- [PATCH v5 08/22] target/arm: Implement the GMI instruction, Richard Henderson, 2019/10/11
- [PATCH v5 09/22] target/arm: Implement the SUBP instruction, Richard Henderson, 2019/10/11
- [PATCH v5 10/22] target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY, Richard Henderson, 2019/10/11
- [PATCH v5 12/22] target/arm: Implement the STGP instruction, Richard Henderson, 2019/10/11
- [PATCH v5 11/22] target/arm: Implement LDG, STG, ST2G instructions, Richard Henderson, 2019/10/11
- [PATCH v5 13/22] target/arm: Implement the LDGM and STGM instructions, Richard Henderson, 2019/10/11
- [PATCH v5 14/22] target/arm: Implement the access tag cache flushes, Richard Henderson, 2019/10/11
- [PATCH v5 16/22] target/arm: Implement data cache set allocation tags, Richard Henderson, 2019/10/11
- [PATCH v5 15/22] target/arm: Clean address for DC ZVA, Richard Henderson, 2019/10/11
- [PATCH v5 17/22] target/arm: Set PSTATE.TCO on exception entry, Richard Henderson, 2019/10/11