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Re: [PATCH 4/5] aspeed/i2c: Add support for DMA transfers
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From: |
Joel Stanley |
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Subject: |
Re: [PATCH 4/5] aspeed/i2c: Add support for DMA transfers |
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Date: |
Wed, 16 Oct 2019 11:24:53 +0000 |
On Wed, 16 Oct 2019 at 08:50, Cédric Le Goater <address@hidden> wrote:
>
> The I2C controller of the Aspeed AST2500 and AST2600 SoCs supports DMA
> transfers to and from DRAM.
>
> A pair of registers defines the buffer address and the length of the
> DMA transfer. The address should be aligned on 4 bytes and the maximum
> length should not exceed 4K. The receive or transmit DMA transfer can
> then be initiated with specific bits in the Command/Status register of
> the controller.
>
> Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>