Re: [PATCH v3 0/4] arm/aspeed: Watchdog and SDRAM fixes

[Peter Maydell]

On Thu, 14 Nov 2019 at 14:17, Cédric Le Goater <address@hidden> wrote:
> We are preparing, and reviewing, the initial 5.0 patchset
> which will contain the I2C pool buffer model plus the fixes
> Joel and I sent.

OK. I currently have in my 'maybe I should do something with this'
list these patchsets:
aspeed/i2c: Add support for pool and DMA transfer modes
arm/aspeed: Watchdog and SDRAM fixes
aspeed: AST2600 SMC fixes and tacoma-bmc machine
aspeed: rework inter model link properties

(I had a quick scan through and there's nothing in any of
them that looked odd to me, though I haven't done a detailed
review). Should I just assume that you'll send out a rollup
patchset with all of those once 5.0 is out ? Alternatively
I could apply them to the target-arm.for-5.0 branch I'm
currently keeping, which will become the first target-arm
pullreq once 5.0 reopens, if you prefer (and if you've
got on-list reviewed-by tags for them all).

thanks
-- PMM