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Re: gicv2 virtual interface alias base address

From: Jose Martins
Subject: Re: gicv2 virtual interface alias base address
Date: Thu, 6 Feb 2020 19:05:46 +0000

Thank you for the clarification Peter. From what I gather from your
explanation, the functionality might be present in the GIC IP but the
SoC designer might choose not to actually expose it in the platform
memory map. But do you see any specific reason why an SoC designer
might do this? Also, in the case of the virt board, and since support
for this is present in other qemu platforms, is there a specific
reason not to include it?

thanks once again

On Thu, 6 Feb 2020 at 17:51, Peter Maydell <address@hidden> wrote:
> On Wed, 5 Feb 2020 at 18:32, Jose Martins <address@hidden> wrote:
> >
> > Gicv2 specification describes a mandatory global alias region through
> > which any virtual interface can be accessed by any cpu. Looking at
> > arm_gic_realize function this region seems to be implemented ( /*Extra
> > core-specific regions for virtual interfaces. This is required by the
> > GICv2 specification */). However, I cant figure out what would be its
> > based address on the memory map. I'm using the virt platform. Can
> > anyone help me with this?
> These are required by the GIC specification, but there's nothing
> that requires any particular SoC or board to actually expose them
> to the programmer. The 'virt' board does not map these. What
> you get is the GICH_* virtual interface control registers at
> 0x08030000, and the GICV_* virtual CPU interface at 0x08040000.
> In both cases the registers apply to the current CPU (ie the CPU
> you access them from); there is no direct access to another CPU's
> GIC interfaces.
> (Our GIC model provides the for-each-core memory regions because
> a few of the boards we model (eg one of the xilinx boards) provide
> that facility in hardware.)
> thanks
> -- PMM

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