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Re: [PATCH 10/13] target/arm: Implement ARMv8.4-PMU extension

From: Richard Henderson
Subject: Re: [PATCH 10/13] target/arm: Implement ARMv8.4-PMU extension
Date: Tue, 11 Feb 2020 10:49:17 -0800
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1

On 2/11/20 9:37 AM, Peter Maydell wrote:
> The ARMv8.4-PMU extension adds:
>  * one new required event, STALL
>  * one new system register PMMIR_EL1
> (There are also some more L1-cache related events, but since
> we don't implement any cache we don't provide these, in the
> same way we don't provide the base-PMUv3 cache events.)
> The STALL event "counts every attributable cycle on which no
> attributable instruction or operation was sent for execution on this
> PE".  QEMU doesn't stall in this sense, so this is another
> always-reads-zero event.
> The PMMIR_EL1 register is a read-only register providing
> implementation-specific information about the PMU; currently it has
> only one field, SLOTS, which defines behaviour of the STALL_SLOT PMU
> event.  Since QEMU doesn't implement the STALL_SLOT event, we can
> validly make the register read zero.
> Signed-off-by: Peter Maydell <address@hidden>
> ---
>  target/arm/cpu.h    | 18 ++++++++++++++++++
>  target/arm/helper.c | 22 +++++++++++++++++++++-
>  2 files changed, 39 insertions(+), 1 deletion(-)

Reviewed-by: Richard Henderson <address@hidden>


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