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Re: [PATCH 08/13] target/arm: Add _aa64_ and _any_ versions of pmu_8_1 i


From: Philippe Mathieu-Daudé
Subject: Re: [PATCH 08/13] target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks
Date: Wed, 12 Feb 2020 07:56:16 +0100
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1

On 2/11/20 6:37 PM, Peter Maydell wrote:
Add the 64-bit version of the "is this a v8.1 PMUv3?"
ID register check function, and the _any_ version that
checks for either AArch32 or AArch64 support. We'll use
this in a later commit.

We don't (yet) do any isar_feature checks on ID_AA64DFR1_EL1,
but we move id_aa64dfr1 into the ARMISARegisters struct with
id_aa64dfr0, for consistency.

Signed-off-by: Peter Maydell <address@hidden>
---
  target/arm/cpu.h    | 15 +++++++++++++--
  target/arm/cpu.c    |  3 ++-
  target/arm/cpu64.c  |  6 +++---
  target/arm/helper.c | 12 +++++++-----
  4 files changed, 25 insertions(+), 11 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index b55f6c8b7d3..2b3124fd76b 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -871,6 +871,8 @@ struct ARMCPU {
          uint64_t id_aa64pfr1;
          uint64_t id_aa64mmfr0;
          uint64_t id_aa64mmfr1;
+        uint64_t id_aa64dfr0;
+        uint64_t id_aa64dfr1;
      } isar;
      uint32_t midr;
      uint32_t revidr;
@@ -887,8 +889,6 @@ struct ARMCPU {
      uint32_t id_mmfr2;
      uint32_t id_mmfr3;
      uint32_t id_mmfr4;
-    uint64_t id_aa64dfr0;
-    uint64_t id_aa64dfr1;
      uint64_t id_aa64afr0;
      uint64_t id_aa64afr1;
      uint32_t dbgdidr;
@@ -3728,6 +3728,12 @@ static inline bool isar_feature_aa64_bti(const 
ARMISARegisters *id)
      return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
  }
+static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id)
+{
+    return FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&
+        FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;

FIELD_EX64()

+}
+
  /*
   * Feature tests for "does this exist in either 32-bit or 64-bit?"
   */
@@ -3741,6 +3747,11 @@ static inline bool isar_feature_any_predinv(const 
ARMISARegisters *id)
      return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id);
  }
+static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id)
+{
+    return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id);
+}
+
  /*
   * Forward to the above feature tests given an ARMCPU pointer.
   */

I'm not sure why, I can't apply this patch locally, but this might be a problem with my smtp setup (I am having some mails oddly re-encoded).

Applying: target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks
error: patch failed: target/arm/cpu.h:3741
error: target/arm/cpu.h: patch does not apply
Patch failed at 0008 target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index ac0c96322d1..df44df1a43a 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1602,7 +1602,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error 
**errp)
                  cpu);
  #endif
      } else {
-        cpu->id_aa64dfr0 = FIELD_DP32(cpu->id_aa64dfr0, ID_AA64DFR0, PMUVER, 
0);
+        cpu->isar.id_aa64dfr0 =
+            FIELD_DP32(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0);

FIELD_EX64()

          cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 
0);
          cpu->pmceid0 = 0;
          cpu->pmceid1 = 0;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index f8fda7e0988..4b4b134ef84 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -135,7 +135,7 @@ static void aarch64_a57_initfn(Object *obj)
      cpu->isar.id_isar5 = 0x00011121;
      cpu->isar.id_isar6 = 0;
      cpu->isar.id_aa64pfr0 = 0x00002222;
-    cpu->id_aa64dfr0 = 0x10305106;
+    cpu->isar.id_aa64dfr0 = 0x10305106;
      cpu->isar.id_aa64isar0 = 0x00011120;
      cpu->isar.id_aa64mmfr0 = 0x00001124;
      cpu->dbgdidr = 0x3516d000;
@@ -189,7 +189,7 @@ static void aarch64_a53_initfn(Object *obj)
      cpu->isar.id_isar5 = 0x00011121;
      cpu->isar.id_isar6 = 0;
      cpu->isar.id_aa64pfr0 = 0x00002222;
-    cpu->id_aa64dfr0 = 0x10305106;
+    cpu->isar.id_aa64dfr0 = 0x10305106;
      cpu->isar.id_aa64isar0 = 0x00011120;
      cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
      cpu->dbgdidr = 0x3516d000;
@@ -241,7 +241,7 @@ static void aarch64_a72_initfn(Object *obj)
      cpu->isar.id_isar4 = 0x00011142;
      cpu->isar.id_isar5 = 0x00011121;
      cpu->isar.id_aa64pfr0 = 0x00002222;
-    cpu->id_aa64dfr0 = 0x10305106;
+    cpu->isar.id_aa64dfr0 = 0x10305106;
      cpu->isar.id_aa64isar0 = 0x00011120;
      cpu->isar.id_aa64mmfr0 = 0x00001124;
      cpu->dbgdidr = 0x3516d000;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ca0bf3402ca..9537785104e 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -25,6 +25,7 @@
  #include "hw/semihosting/semihost.h"
  #include "sysemu/cpus.h"
  #include "sysemu/kvm.h"
+#include "sysemu/tcg.h"
  #include "qemu/range.h"
  #include "qapi/qapi-commands-machine-target.h"
  #include "qapi/error.h"
@@ -5771,9 +5772,10 @@ static void define_debug_regs(ARMCPU *cpu)
       * check that if they both exist then they agree.
       */
      if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
-        assert(FIELD_EX32(cpu->id_aa64dfr0, ID_AA64DFR0, BRPS) == brps);
-        assert(FIELD_EX32(cpu->id_aa64dfr0, ID_AA64DFR0, WRPS) == wrps);
-        assert(FIELD_EX32(cpu->id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) == 
ctx_cmps);
+        assert(FIELD_EX32(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) == brps);
+        assert(FIELD_EX32(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) == wrps);
+        assert(FIELD_EX32(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS)
+               == ctx_cmps);

FIELD_EX64()

      }
define_one_arm_cp_reg(cpu, &dbgdidr);
@@ -6395,12 +6397,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
                .access = PL1_R, .type = ARM_CP_CONST,
                .accessfn = access_aa64_tid3,
-              .resetvalue = cpu->id_aa64dfr0 },
+              .resetvalue = cpu->isar.id_aa64dfr0 },
              { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
                .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
                .access = PL1_R, .type = ARM_CP_CONST,
                .accessfn = access_aa64_tid3,
-              .resetvalue = cpu->id_aa64dfr1 },
+              .resetvalue = cpu->isar.id_aa64dfr1 },
              { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
                .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,
                .access = PL1_R, .type = ARM_CP_CONST,


Using 64bit macros:
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>




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