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Re: [RESEND RFC PATCH v2 2/2] target/arm: Support NMI injection

From: Gavin Shan
Subject: Re: [RESEND RFC PATCH v2 2/2] target/arm: Support NMI injection
Date: Fri, 14 Feb 2020 17:23:16 +1100
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0

On 2/13/20 10:11 PM, Peter Maydell wrote:
On Wed, 5 Feb 2020 at 11:06, Gavin Shan <address@hidden> wrote:

This supports QMP/HMP "nmi" command by injecting SError interrupt to
guest, which is expected to crash with that. Currently, It's supported
on two CPU models: "host" and "max".

Signed-off-by: Gavin Shan <address@hidden>
  hw/arm/virt.c          | 18 ++++++++++++++++
  target/arm/cpu-qom.h   |  1 +
  target/arm/cpu.c       | 48 ++++++++++++++++++++++++++++++++++++++++++
  target/arm/cpu64.c     | 25 ++++++++++++++++++----
  target/arm/internals.h |  8 +++++++
  5 files changed, 96 insertions(+), 4 deletions(-)

A few quick general notes:

(1) as I mentioned on the cover letter, the mechanism
for injecting an SError/async external abort into the
CPU should be a qemu_irq line, like FIQ/IRQ, not a
special-purpose method on the CPU object.

(2) for function naming, there's a dividing line between:
  * code that implements the (unfortunately x86-centric)
    monitor command named "nmi"; these functions can have
    names with 'nmi' in them
  * code which implements the actual mechanism of 'deliver
    an SError to the CPU'; these functions should not
    have 'nmi' in the name or mention nmi, because nmi is
    not a concept in the Arm architecture

(3) Before we expose 'nmi' to users as something that
delivers an SError, we need to think about the interactions
with RAS, because currently we also use SError to say
"there was an error in the host memory you're using",
and we might in future want to use SError for proper
emulated RAS. We don't want to paint ourselves into a
corner by grabbing SError exclusively for 'nmi'.

Hi Peter, Thanks for the nice details. I just posted v3 to address
(1) and (2).

For (3), I'm not sure. It seems we need some registers to record the
details on why the SError is raised. For ARMv8 with RAS extension is
supported, VSESR_EL2 can be used. Otherwise, we probably need some
space in ESR_EL1. For aarch32, DFSR might be the alternative. With
more details about the cause, the "NMI" and other errors can be

May I ask if the SError is going to be triggered by simulated device
or real one, or both in future? If it's corresponding to host memory
error, it seems it should be triggered by a real hardware. In this case,
the error should be intercepted and then delivered to guest. I need
more details how the SError will be used for RAS.


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