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Re: [PATCH v3 3/7] target/arm: Honor the HCR_EL2.TSW bit
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From: |
Peter Maydell |
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Subject: |
Re: [PATCH v3 3/7] target/arm: Honor the HCR_EL2.TSW bit |
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Date: |
Tue, 25 Feb 2020 11:46:31 +0000 |
On Tue, 18 Feb 2020 at 19:10, Richard Henderson
<address@hidden> wrote:
>
> These bits trap EL1 access to set/way cache maintenance insns.
>
> Buglink: https://bugs.launchpad.net/bugs/1863685
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> target/arm/helper.c | 22 ++++++++++++++++------
> 1 file changed, 16 insertions(+), 6 deletions(-)
Reviewed-by: Peter Maydell <address@hidden>
thanks
-- PMM
- [PATCH v3 0/7] target/arm: Honor more HCR_EL2 traps, Richard Henderson, 2020/02/18
- [PATCH v3 1/7] target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn, Richard Henderson, 2020/02/18
- [PATCH v3 3/7] target/arm: Honor the HCR_EL2.TSW bit, Richard Henderson, 2020/02/18
- Re: [PATCH v3 3/7] target/arm: Honor the HCR_EL2.TSW bit,
Peter Maydell <=
- [PATCH v3 2/7] target/arm: Honor the HCR_EL2.{TVM,TRVM} bits, Richard Henderson, 2020/02/18
- [PATCH v3 4/7] target/arm: Honor the HCR_EL2.TACR bit, Richard Henderson, 2020/02/18
- [PATCH v3 6/7] target/arm: Honor the HCR_EL2.TPU bit, Richard Henderson, 2020/02/18
- [PATCH v3 5/7] target/arm: Honor the HCR_EL2.TPCP bit, Richard Henderson, 2020/02/18
- [PATCH v3 7/7] target/arm: Honor the HCR_EL2.TTLB bit, Richard Henderson, 2020/02/18