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[PATCH v2 005/100] target/arm: Rearrange {sve, fp}_check_access assert
From: |
Richard Henderson |
Subject: |
[PATCH v2 005/100] target/arm: Rearrange {sve, fp}_check_access assert |
Date: |
Wed, 17 Jun 2020 21:25:09 -0700 |
We want to ensure that access is checked by the time we ask
for a specific fp/vector register. We want to ensure that
we do not emit two lots of code to raise an exception.
But sometimes it's difficult to cleanly organize the code
such that we never pass through sve_check_access exactly once.
Allow multiple calls so long as the result is true, that is,
no exception to be raised.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.h | 1 +
target/arm/translate-a64.c | 27 ++++++++++++++++-----------
2 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 62ed5c4780..f6a9e1054b 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -63,6 +63,7 @@ typedef struct DisasContext {
* that it is set at the point where we actually touch the FP regs.
*/
bool fp_access_checked;
+ bool sve_access_checked;
/* ARMv8 single-step state (this is distinct from the QEMU gdbstub
* single-step support).
*/
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index a0e72ad694..b80ee9f734 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1083,18 +1083,18 @@ static void do_vec_ld(DisasContext *s, int destidx, int
element,
* unallocated-encoding checks (otherwise the syndrome information
* for the resulting exception will be incorrect).
*/
-static inline bool fp_access_check(DisasContext *s)
+static bool fp_access_check(DisasContext *s)
{
- assert(!s->fp_access_checked);
- s->fp_access_checked = true;
+ if (s->fp_excp_el) {
+ assert(!s->fp_access_checked);
+ s->fp_access_checked = true;
- if (!s->fp_excp_el) {
- return true;
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
+ syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
+ return false;
}
-
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
- syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
- return false;
+ s->fp_access_checked = true;
+ return true;
}
/* Check that SVE access is enabled. If it is, return true.
@@ -1103,10 +1103,14 @@ static inline bool fp_access_check(DisasContext *s)
bool sve_access_check(DisasContext *s)
{
if (s->sve_excp_el) {
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_sve_access_trap(),
- s->sve_excp_el);
+ assert(!s->sve_access_checked);
+ s->sve_access_checked = true;
+
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
+ syn_sve_access_trap(), s->sve_excp_el);
return false;
}
+ s->sve_access_checked = true;
return fp_access_check(s);
}
@@ -14050,6 +14054,7 @@ static void disas_a64_insn(CPUARMState *env,
DisasContext *s)
s->base.pc_next += 4;
s->fp_access_checked = false;
+ s->sve_access_checked = false;
if (dc_isar_feature(aa64_bti, s)) {
if (s->base.num_insns == 1) {
--
2.25.1
- [PATCH v2 000/100] target/arm: Implement SVE2, Richard Henderson, 2020/06/18
- [PATCH v2 001/100] tcg: Save/restore vecop_list around minmax fallback, Richard Henderson, 2020/06/18
- [PATCH v2 003/100] target/arm: Split out gen_gvec_fn_zz, Richard Henderson, 2020/06/18
- [PATCH v2 002/100] qemu/int128: Add int128_lshift, Richard Henderson, 2020/06/18
- [PATCH v2 004/100] target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn, Richard Henderson, 2020/06/18
- [PATCH v2 005/100] target/arm: Rearrange {sve, fp}_check_access assert,
Richard Henderson <=
- [PATCH v2 006/100] target/arm: Merge do_vector2_p into do_mov_p, Richard Henderson, 2020/06/18
- [PATCH v2 007/100] target/arm: Clean up 4-operand predicate expansion, Richard Henderson, 2020/06/18
- [PATCH v2 008/100] target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp, Richard Henderson, 2020/06/18
- [PATCH v2 009/100] target/arm: Split out gen_gvec_ool_zzzp, Richard Henderson, 2020/06/18
- [PATCH v2 011/100] target/arm: Split out gen_gvec_ool_zzp, Richard Henderson, 2020/06/18
- [PATCH v2 012/100] target/arm: Split out gen_gvec_ool_zzz, Richard Henderson, 2020/06/18
- [PATCH v2 010/100] target/arm: Merge helper_sve_clr_* and helper_sve_movz_*, Richard Henderson, 2020/06/18
- [PATCH v2 013/100] target/arm: Split out gen_gvec_ool_zz, Richard Henderson, 2020/06/18
- [PATCH v2 014/100] target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2, Richard Henderson, 2020/06/18
- [PATCH v2 016/100] target/arm: Implement SVE2 Integer Multiply - Unpredicated, Richard Henderson, 2020/06/18