Re: [PATCH v8 00/45] target/arm: Implement ARMv8.5-MemTag, system mode

[no-reply]

Patchew URL: 
20200623193658.623279-1-richard.henderson@linaro.org/">https://patchew.org/QEMU/20200623193658.623279-1-richard.henderson@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [PATCH v8 00/45] target/arm: Implement ARMv8.5-MemTag, system mode
Type: series
Message-id: 20200623193658.623279-1-richard.henderson@linaro.org

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

From https://github.com/patchew-project/qemu
 * [new tag]         
patchew/20200623193658.623279-1-richard.henderson@linaro.org -> 
patchew/20200623193658.623279-1-richard.henderson@linaro.org
Switched to a new branch 'test'
1231ec5 target/arm: Enable MTE
caf48f0 target/arm: Add allocation tag storage for system mode
86926ba target/arm: Create tagged ram when MTE is enabled
dc24d39 target/arm: Cache the Tagged bit for a page in MemTxAttrs
b3fdcfe target/arm: Always pass cacheattr to get_phys_addr
52dae54 target/arm: Set PSTATE.TCO on exception entry
9d92dcf target/arm: Implement data cache set allocation tags
985b40f target/arm: Complete TBI clearing for user-only for SVE
d22a925 target/arm: Add mte helpers for sve scatter/gather memory ops
26d1ba5 target/arm: Handle TBI for sve scalar + int memory ops
5dc33b2 target/arm: Add mte helpers for sve scalar + int ff/nf loads
457edf5 target/arm: Add mte helpers for sve scalar + int stores
7e68033 target/arm: Add mte helpers for sve scalar + int loads
df0ee49 target/arm: Add arm_tlb_bti_gp
46870d1 target/arm: Tidy trans_LD1R_zpri
661859f target/arm: Use mte_check1 for sve LD1R
c067218 target/arm: Use mte_checkN for sve unpredicated stores
abbc5d1 target/arm: Use mte_checkN for sve unpredicated loads
da2c53d target/arm: Add helper_mte_check_zva
a947bd3 target/arm: Implement helper_mte_checkN
017e09e target/arm: Implement helper_mte_check1
060a546 target/arm: Add gen_mte_checkN
349cca3 target/arm: Add gen_mte_check1
bcb99d2 target/arm: Move regime_tcr to internals.h
3e1b548 target/arm: Move regime_el to internals.h
e03f1b4 target/arm: Implement the access tag cache flushes
d6ad4b5 target/arm: Implement the LDGM, STGM, STZGM instructions
e16594d target/arm: Simplify DC_ZVA
dc1d79a target/arm: Restrict the values of DCZID.BS under TCG
1291525 target/arm: Implement the STGP instruction
1b4d84d target/arm: Implement LDG, STG, ST2G instructions
54c306b target/arm: Define arm_cpu_do_unaligned_access for user-only
56adc0c target/arm: Implement the SUBP instruction
e1d7cf7 target/arm: Implement the GMI instruction
2890f30 target/arm: Implement the ADDG, SUBG instructions
912b9bf target/arm: Revise decoding for disas_add_sub_imm
63945d2 target/arm: Implement the IRG instruction
22de2b3 target/arm: Add MTE bits to tb_flags
45f22ac target/arm: Add MTE system registers
2fbb1da target/arm: Add DISAS_UPDATE_NOCHAIN
e4d0611 target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT
d0f228b target/arm: Add support for MTE to HCR_EL2 and SCR_EL3
a5b3055 target/arm: Add support for MTE to SCTLR_ELx
abdfb70 target/arm: Improve masking of SCR RES0 bits
40707f0 target/arm: Add isar tests for mte

=== OUTPUT BEGIN ===
1/45 Checking commit 40707f09f121 (target/arm: Add isar tests for mte)
2/45 Checking commit abdfb70dea3d (target/arm: Improve masking of SCR RES0 bits)
3/45 Checking commit a5b305518974 (target/arm: Add support for MTE to SCTLR_ELx)
4/45 Checking commit d0f228b9f5f4 (target/arm: Add support for MTE to HCR_EL2 
and SCR_EL3)
5/45 Checking commit e4d06118aebc (target/arm: Rename DISAS_UPDATE to 
DISAS_UPDATE_EXIT)
6/45 Checking commit 2fbb1dafd99c (target/arm: Add DISAS_UPDATE_NOCHAIN)
7/45 Checking commit 45f22acdd599 (target/arm: Add MTE system registers)
8/45 Checking commit 22de2b35721f (target/arm: Add MTE bits to tb_flags)
9/45 Checking commit 63945d282302 (target/arm: Implement the IRG instruction)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#45: 
new file mode 100644

total: 0 errors, 1 warnings, 120 lines checked

Patch 9/45 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/45 Checking commit 912b9bf152c9 (target/arm: Revise decoding for 
disas_add_sub_imm)
11/45 Checking commit 2890f308b67c (target/arm: Implement the ADDG, SUBG 
instructions)
12/45 Checking commit e1d7cf7b3195 (target/arm: Implement the GMI instruction)
13/45 Checking commit 56adc0c58443 (target/arm: Implement the SUBP instruction)
14/45 Checking commit 54c306b84778 (target/arm: Define 
arm_cpu_do_unaligned_access for user-only)
15/45 Checking commit 1b4d84d4bf40 (target/arm: Implement LDG, STG, ST2G 
instructions)
16/45 Checking commit 129152540330 (target/arm: Implement the STGP instruction)
17/45 Checking commit dc1d79a46ea9 (target/arm: Restrict the values of DCZID.BS 
under TCG)
18/45 Checking commit e16594db4ee6 (target/arm: Simplify DC_ZVA)
19/45 Checking commit d6ad4b51f761 (target/arm: Implement the LDGM, STGM, STZGM 
instructions)
20/45 Checking commit e03f1b492eb8 (target/arm: Implement the access tag cache 
flushes)
21/45 Checking commit 3e1b548f5665 (target/arm: Move regime_el to internals.h)
22/45 Checking commit bcb99d2cb0d5 (target/arm: Move regime_tcr to internals.h)
23/45 Checking commit 349cca39015e (target/arm: Add gen_mte_check1)
24/45 Checking commit 060a546b2de1 (target/arm: Add gen_mte_checkN)
25/45 Checking commit 017e09edd952 (target/arm: Implement helper_mte_check1)
26/45 Checking commit a947bd38a095 (target/arm: Implement helper_mte_checkN)
27/45 Checking commit da2c53dcc0e2 (target/arm: Add helper_mte_check_zva)
28/45 Checking commit abbc5d1dd1f3 (target/arm: Use mte_checkN for sve 
unpredicated loads)
29/45 Checking commit c067218f4474 (target/arm: Use mte_checkN for sve 
unpredicated stores)
30/45 Checking commit 661859ff9984 (target/arm: Use mte_check1 for sve LD1R)
31/45 Checking commit 46870d1ed93b (target/arm: Tidy trans_LD1R_zpri)
32/45 Checking commit df0ee49681ee (target/arm: Add arm_tlb_bti_gp)
33/45 Checking commit 7e68033a5c5e (target/arm: Add mte helpers for sve scalar 
+ int loads)
34/45 Checking commit 457edf568b72 (target/arm: Add mte helpers for sve scalar 
+ int stores)
35/45 Checking commit 5dc33b2a8bb2 (target/arm: Add mte helpers for sve scalar 
+ int ff/nf loads)
36/45 Checking commit 26d1ba548fc0 (target/arm: Handle TBI for sve scalar + int 
memory ops)
37/45 Checking commit d22a9255942c (target/arm: Add mte helpers for sve 
scatter/gather memory ops)
38/45 Checking commit 985b40fb259c (target/arm: Complete TBI clearing for 
user-only for SVE)
ERROR: spaces required around that '*' (ctx:VxV)
#42: FILE: target/arm/sve_helper.c:3978:
+        (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra);                            \
                ^

total: 1 errors, 0 warnings, 37 lines checked

Patch 38/45 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

39/45 Checking commit 9d92dcf8187b (target/arm: Implement data cache set 
allocation tags)
40/45 Checking commit 52dae54ca0f4 (target/arm: Set PSTATE.TCO on exception 
entry)
41/45 Checking commit b3fdcfe39e1d (target/arm: Always pass cacheattr to 
get_phys_addr)
42/45 Checking commit dc24d3963608 (target/arm: Cache the Tagged bit for a page 
in MemTxAttrs)
43/45 Checking commit 86926ba74d36 (target/arm: Create tagged ram when MTE is 
enabled)
44/45 Checking commit caf48f000954 (target/arm: Add allocation tag storage for 
system mode)
45/45 Checking commit 1231ec5cb04a (target/arm: Enable MTE)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
20200623193658.623279-1-richard.henderson@linaro.org/testing.checkpatch/?type=message">http://patchew.org/logs/20200623193658.623279-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
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