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[PATCH v9 13/46] target/arm: Implement the SUBP instruction
From: |
Richard Henderson |
Subject: |
[PATCH v9 13/46] target/arm: Implement the SUBP instruction |
Date: |
Thu, 25 Jun 2020 20:31:11 -0700 |
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Fix extraction length.
---
target/arm/translate-a64.c | 24 ++++++++++++++++++++++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index ee9dfa8e43..abbcdbb53a 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -5315,19 +5315,39 @@ static void handle_crc32(DisasContext *s,
*/
static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
{
- unsigned int sf, rm, opcode, rn, rd;
+ unsigned int sf, rm, opcode, rn, rd, setflag;
sf = extract32(insn, 31, 1);
+ setflag = extract32(insn, 29, 1);
rm = extract32(insn, 16, 5);
opcode = extract32(insn, 10, 6);
rn = extract32(insn, 5, 5);
rd = extract32(insn, 0, 5);
- if (extract32(insn, 29, 1)) {
+ if (setflag && opcode != 0) {
unallocated_encoding(s);
return;
}
switch (opcode) {
+ case 0: /* SUBP(S) */
+ if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) {
+ goto do_unallocated;
+ } else {
+ TCGv_i64 tcg_n, tcg_m, tcg_d;
+
+ tcg_n = read_cpu_reg_sp(s, rn, true);
+ tcg_m = read_cpu_reg_sp(s, rm, true);
+ tcg_gen_sextract_i64(tcg_n, tcg_n, 0, 56);
+ tcg_gen_sextract_i64(tcg_m, tcg_m, 0, 56);
+ tcg_d = cpu_reg(s, rd);
+
+ if (setflag) {
+ gen_sub_CC(true, tcg_d, tcg_n, tcg_m);
+ } else {
+ tcg_gen_sub_i64(tcg_d, tcg_n, tcg_m);
+ }
+ }
+ break;
case 2: /* UDIV */
handle_div(s, false, sf, rm, rn, rd);
break;
--
2.25.1
- [PATCH v9 03/46] target/arm: Add support for MTE to SCTLR_ELx, (continued)
- [PATCH v9 03/46] target/arm: Add support for MTE to SCTLR_ELx, Richard Henderson, 2020/06/25
- [PATCH v9 04/46] target/arm: Add support for MTE to HCR_EL2 and SCR_EL3, Richard Henderson, 2020/06/25
- [PATCH v9 05/46] target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT, Richard Henderson, 2020/06/25
- [PATCH v9 07/46] target/arm: Add MTE system registers, Richard Henderson, 2020/06/25
- [PATCH v9 06/46] target/arm: Add DISAS_UPDATE_NOCHAIN, Richard Henderson, 2020/06/25
- [PATCH v9 08/46] target/arm: Add MTE bits to tb_flags, Richard Henderson, 2020/06/25
- [PATCH v9 09/46] target/arm: Implement the IRG instruction, Richard Henderson, 2020/06/25
- [PATCH v9 11/46] target/arm: Implement the ADDG, SUBG instructions, Richard Henderson, 2020/06/25
- [PATCH v9 10/46] target/arm: Revise decoding for disas_add_sub_imm, Richard Henderson, 2020/06/25
- [PATCH v9 12/46] target/arm: Implement the GMI instruction, Richard Henderson, 2020/06/25
- [PATCH v9 13/46] target/arm: Implement the SUBP instruction,
Richard Henderson <=
- [PATCH v9 14/46] target/arm: Define arm_cpu_do_unaligned_access for user-only, Richard Henderson, 2020/06/25
- [PATCH v9 15/46] target/arm: Implement LDG, STG, ST2G instructions, Richard Henderson, 2020/06/25
- [PATCH v9 16/46] target/arm: Implement the STGP instruction, Richard Henderson, 2020/06/25
- [PATCH v9 17/46] target/arm: Restrict the values of DCZID.BS under TCG, Richard Henderson, 2020/06/25
- [PATCH v9 18/46] target/arm: Simplify DC_ZVA, Richard Henderson, 2020/06/25
- [PATCH v9 19/46] target/arm: Implement the LDGM, STGM, STZGM instructions, Richard Henderson, 2020/06/25
- [PATCH v9 21/46] target/arm: Move regime_el to internals.h, Richard Henderson, 2020/06/25
- [PATCH v9 20/46] target/arm: Implement the access tag cache flushes, Richard Henderson, 2020/06/25
- [PATCH v9 22/46] target/arm: Move regime_tcr to internals.h, Richard Henderson, 2020/06/25
- [PATCH v9 23/46] target/arm: Add gen_mte_check1, Richard Henderson, 2020/06/25