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Re: [PATCH] target/arm: Fix decode of {LD,ST}RA[AB] instructions

From: Peter Collingbourne
Subject: Re: [PATCH] target/arm: Fix decode of {LD,ST}RA[AB] instructions
Date: Tue, 4 Aug 2020 10:28:05 -0700

On Tue, Aug 4, 2020 at 8:41 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
> On 8/3/20 5:21 PM, Peter Collingbourne wrote:
> > On Mon, Aug 3, 2020 at 3:27 PM Peter Collingbourne <pcc@google.com> wrote:
> >>
> >> These instructions use zero as the discriminator, not SP.
> >
> > Oh, there is no such thing as STRAA/STRAB. I must have been confused
> > by the name of the function, disas_ldst_pac. I will send a v2 with a
> > fixed commit message, and another patch to rename the function to
> > disas_ld_pac.
> It's called decode_ldst_pac because the Arm ARM section is called "Load/store
> register (pac)".  Page C4-311 in the F.a revision.
> But yes, there are only loads defined in the section.

I see. Arguably the ARM ARM section is misnamed then. There is a
sibling section named "Load register (literal)", so there is precedent
for naming a section after the types of instructions that are actually
supported. I will send mail to errata@arm.com to see if the section
can be renamed.


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