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Re: [PATCH v2 for-5.1?] target/arm: Fix Rt/Rt2 in ESR_ELx for copro trap

From: Peter Maydell
Subject: Re: [PATCH v2 for-5.1?] target/arm: Fix Rt/Rt2 in ESR_ELx for copro traps from AArch32 to 64
Date: Wed, 5 Aug 2020 17:32:28 +0100

On Wed, 5 Aug 2020 at 16:26, Richard Henderson
<richard.henderson@linaro.org> wrote:
> On 8/4/20 12:39 PM, Peter Maydell wrote:
> > When a coprocessor instruction in an  AArch32 guest traps to AArch32
> > Hyp mode, the syndrome register (HSR) includes Rt and Rt2 fields
> > which are simply copies of the Rt and Rt2 fields from the trapped
> > instruction.  However, if the instruction is trapped from AArch32 to
> > an AArch64 higher exception level, the Rt and Rt2 fields in the
> > syndrome register (ESR_ELx) must be the AArch64 view of the register.
> > This makes a difference if the AArch32 guest was in a mode other than
> > User or System and it was using r13 or r14, or if it was in FIQ mode
> > and using r8-r14.
> >
> > We don't know at translate time which AArch32 CPU mode we are in, so
> > we leave the values we generate in our prototype syndrome register
> > value at translate time as the raw Rt/Rt2 from the instruction, and
> > instead correct them to the AArch64 view when we find we need to take
> > an exception from AArch32 to AArch64 with one of these syndrome
> > values.
> >
> > Fixes: https://bugs.launchpad.net/qemu/+bug/1879587
> > Reported-by: Julien Freche <julien@bedrocksystems.com>
> > Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> > ---
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Thanks; applied to master for 5.1.

-- PMM

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