Re: Arm Cortex M4 floating point

[Peter Maydell]

On Tue, 18 Aug 2020 at 15:48, Mircea Cociuba <cociuba_mircea@yahoo.com> wrote:
>
> Thank you very much Peter,
> I will try this first thing in the morning,
>
> But before I try this, if the register is memory mapped, the stelaris memory 
> map has no FPU.
> Is the FPU always at core level at the same address?

The registers like the CPACR are memory mapped as part of the
CPU itself[*]. They're architecturally always in the same place
regardless of what board is being used.

[*] in QEMU's code internally we actually implement them
inside our NVIC model, which is a slightly odd place to
do it, but this isn't visible to the guest which just sees
the registers in the right places.

thanks
-- PMM