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[PATCH 10/10] target/arm: Fix writing to FPSCR.FZ16 on M-profile
From: |
Peter Maydell |
Subject: |
[PATCH 10/10] target/arm: Fix writing to FPSCR.FZ16 on M-profile |
Date: |
Mon, 12 Oct 2020 16:37:46 +0100 |
The M-profile specific part of the sanitizing of the value to
be written to the FPSCR used a mask which always zeroed bit 19,
which is FZ16. This is incorrect when the CPU supports 16-bit
floating point arithmetic, because the bit should be writeable.
Code earlier in the function already handles making this bit be RES0
if the CPU doesn't implement the FP16 feature, so we can simply stop
masking it out for M-profile.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/vfp_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 350150adbf1..4b0bb2bacfb 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -198,13 +198,14 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
if (arm_feature(env, ARM_FEATURE_M)) {
/*
- * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits
+ * M profile FPSCR is RES0 for the QC, STRIDE, LEN bits
* and also for the trapped-exception-handling bits IxE.
* From v8.1M with the low-overhead-loop extension bits
* [18:16] are used for LTPSIZE and (since we don't implement
* MVE) always read as 4 and ignore writes.
+ * FZ16 has already been handled as RES0 above if needed.
*/
- val &= 0xf7c0009f;
+ val &= 0xf7c8009f;
if (cpu_isar_feature(aa32_lob, cpu)) {
val |= 4 << 16;
}
--
2.20.1
- Re: [PATCH 09/10] target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension, (continued)
[PATCH 05/10] target/arm: Don't allow BLX imm for M-profile, Peter Maydell, 2020/10/12
[PATCH 08/10] target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile, Peter Maydell, 2020/10/12
[PATCH 04/10] target/arm: Make the t32 insn[25:23]=111 group non-overlapping, Peter Maydell, 2020/10/12
[PATCH 06/10] target/arm: Implement v8.1M branch-future insns (as NOPs), Peter Maydell, 2020/10/12
[PATCH 10/10] target/arm: Fix writing to FPSCR.FZ16 on M-profile,
Peter Maydell <=